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1 //===- ARCInstrInfo.cpp - ARC Instruction Information -----------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the ARC implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "ARCInstrInfo.h"
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15 #include "ARC.h"
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16 #include "ARCMachineFunctionInfo.h"
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17 #include "ARCSubtarget.h"
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18 #include "MCTargetDesc/ARCInfo.h"
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19 #include "llvm/CodeGen/MachineFrameInfo.h"
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20 #include "llvm/CodeGen/MachineInstrBuilder.h"
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21 #include "llvm/CodeGen/MachineMemOperand.h"
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22 #include "llvm/Support/Debug.h"
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23 #include "llvm/Support/TargetRegistry.h"
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24
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25 using namespace llvm;
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26
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27 #define GET_INSTRINFO_CTOR_DTOR
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28 #include "ARCGenInstrInfo.inc"
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29
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30 #define DEBUG_TYPE "arc-inst-info"
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31 // Pin the vtable to this file.
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32 void ARCInstrInfo::anchor() {}
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33
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34 ARCInstrInfo::ARCInstrInfo()
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35 : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI() {}
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36
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37 static bool isZeroImm(const MachineOperand &Op) {
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38 return Op.isImm() && Op.getImm() == 0;
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39 }
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40
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41 static bool isLoad(int Opcode) {
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42 return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 ||
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43 Opcode == ARC::LDB_rs9;
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44 }
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45
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46 static bool isStore(int Opcode) {
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47 return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 ||
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48 Opcode == ARC::STB_rs9;
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49 }
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50
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51 /// If the specified machine instruction is a direct
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52 /// load from a stack slot, return the virtual or physical register number of
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53 /// the destination along with the FrameIndex of the loaded stack slot. If
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54 /// not, return 0. This predicate must return 0 if the instruction has
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55 /// any side effects other than loading from the stack slot.
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56 unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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57 int &FrameIndex) const {
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58 int Opcode = MI.getOpcode();
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59 if (isLoad(Opcode)) {
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60 if ((MI.getOperand(1).isFI()) && // is a stack slot
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61 (MI.getOperand(2).isImm()) && // the imm is zero
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62 (isZeroImm(MI.getOperand(2)))) {
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63 FrameIndex = MI.getOperand(1).getIndex();
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64 return MI.getOperand(0).getReg();
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65 }
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66 }
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67 return 0;
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68 }
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69
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70 /// If the specified machine instruction is a direct
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71 /// store to a stack slot, return the virtual or physical register number of
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72 /// the source reg along with the FrameIndex of the loaded stack slot. If
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73 /// not, return 0. This predicate must return 0 if the instruction has
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74 /// any side effects other than storing to the stack slot.
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75 unsigned ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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76 int &FrameIndex) const {
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77 int Opcode = MI.getOpcode();
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78 if (isStore(Opcode)) {
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79 if ((MI.getOperand(1).isFI()) && // is a stack slot
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80 (MI.getOperand(2).isImm()) && // the imm is zero
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81 (isZeroImm(MI.getOperand(2)))) {
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82 FrameIndex = MI.getOperand(1).getIndex();
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83 return MI.getOperand(0).getReg();
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84 }
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85 }
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86 return 0;
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87 }
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88
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89 /// Return the inverse of passed condition, i.e. turning COND_E to COND_NE.
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90 static ARCCC::CondCode GetOppositeBranchCondition(ARCCC::CondCode CC) {
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91 switch (CC) {
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92 default:
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93 llvm_unreachable("Illegal condition code!");
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94 case ARCCC::EQ:
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95 return ARCCC::NE;
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96 case ARCCC::NE:
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97 return ARCCC::EQ;
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98 case ARCCC::LO:
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99 return ARCCC::HS;
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100 case ARCCC::HS:
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101 return ARCCC::LO;
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102 case ARCCC::GT:
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103 return ARCCC::LE;
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104 case ARCCC::GE:
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105 return ARCCC::LT;
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106 case ARCCC::LT:
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107 return ARCCC::GE;
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108 case ARCCC::LE:
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109 return ARCCC::GT;
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110 case ARCCC::HI:
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111 return ARCCC::LS;
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112 case ARCCC::LS:
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113 return ARCCC::HI;
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114 case ARCCC::NZ:
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115 return ARCCC::Z;
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116 case ARCCC::Z:
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117 return ARCCC::NZ;
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118 }
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119 }
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120
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121 static bool isUncondBranchOpcode(int Opc) { return Opc == ARC::BR; }
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122
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123 static bool isCondBranchOpcode(int Opc) {
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124 return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p;
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125 }
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126
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127 static bool isJumpOpcode(int Opc) { return Opc == ARC::J; }
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128
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129 /// Analyze the branching code at the end of MBB, returning
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130 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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131 /// implemented for a target). Upon success, this returns false and returns
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132 /// with the following information in various cases:
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133 ///
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134 /// 1. If this block ends with no branches (it just falls through to its succ)
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135 /// just return false, leaving TBB/FBB null.
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136 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
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137 /// the destination block.
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138 /// 3. If this block ends with a conditional branch and it falls through to a
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139 /// successor block, it sets TBB to be the branch destination block and a
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140 /// list of operands that evaluate the condition. These operands can be
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141 /// passed to other TargetInstrInfo methods to create new branches.
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142 /// 4. If this block ends with a conditional branch followed by an
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143 /// unconditional branch, it returns the 'true' destination in TBB, the
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144 /// 'false' destination in FBB, and a list of operands that evaluate the
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145 /// condition. These operands can be passed to other TargetInstrInfo
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146 /// methods to create new branches.
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147 ///
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148 /// Note that RemoveBranch and InsertBranch must be implemented to support
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149 /// cases where this method returns success.
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150 ///
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151 /// If AllowModify is true, then this routine is allowed to modify the basic
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152 /// block (e.g. delete instructions after the unconditional branch).
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153
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154 bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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155 MachineBasicBlock *&TBB,
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156 MachineBasicBlock *&FBB,
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157 SmallVectorImpl<MachineOperand> &Cond,
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158 bool AllowModify) const {
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159 TBB = FBB = nullptr;
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160 MachineBasicBlock::iterator I = MBB.end();
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161 if (I == MBB.begin())
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162 return false;
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163 --I;
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164
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165 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
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166 // Flag to be raised on unanalyzeable instructions. This is useful in cases
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167 // where we want to clean up on the end of the basic block before we bail
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168 // out.
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169 bool CantAnalyze = false;
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170
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171 // Skip over DEBUG values and predicated nonterminators.
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172 while (I->isDebugValue() || !I->isTerminator()) {
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173 if (I == MBB.begin())
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174 return false;
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175 --I;
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176 }
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177
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178 if (isJumpOpcode(I->getOpcode())) {
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179 // Indirect branches and jump tables can't be analyzed, but we still want
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180 // to clean up any instructions at the tail of the basic block.
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181 CantAnalyze = true;
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182 } else if (isUncondBranchOpcode(I->getOpcode())) {
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183 TBB = I->getOperand(0).getMBB();
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184 } else if (isCondBranchOpcode(I->getOpcode())) {
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185 // Bail out if we encounter multiple conditional branches.
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186 if (!Cond.empty())
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187 return true;
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188
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189 assert(!FBB && "FBB should have been null.");
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190 FBB = TBB;
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191 TBB = I->getOperand(0).getMBB();
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192 Cond.push_back(I->getOperand(1));
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193 Cond.push_back(I->getOperand(2));
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194 Cond.push_back(I->getOperand(3));
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195 } else if (I->isReturn()) {
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196 // Returns can't be analyzed, but we should run cleanup.
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197 CantAnalyze = !isPredicated(*I);
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198 } else {
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199 // We encountered other unrecognized terminator. Bail out immediately.
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200 return true;
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201 }
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202
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203 // Cleanup code - to be run for unpredicated unconditional branches and
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204 // returns.
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205 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||
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206 isJumpOpcode(I->getOpcode()) || I->isReturn())) {
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207 // Forget any previous condition branch information - it no longer
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208 // applies.
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209 Cond.clear();
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210 FBB = nullptr;
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211
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212 // If we can modify the function, delete everything below this
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213 // unconditional branch.
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214 if (AllowModify) {
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215 MachineBasicBlock::iterator DI = std::next(I);
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216 while (DI != MBB.end()) {
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217 MachineInstr &InstToDelete = *DI;
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218 ++DI;
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219 InstToDelete.eraseFromParent();
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220 }
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221 }
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222 }
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223
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224 if (CantAnalyze)
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225 return true;
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226
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227 if (I == MBB.begin())
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228 return false;
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229
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230 --I;
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231 }
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232
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233 // We made it past the terminators without bailing out - we must have
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234 // analyzed this branch successfully.
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235 return false;
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236 }
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237
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238 unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
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239 int *BytesRemoved) const {
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240 assert(!BytesRemoved && "Code size not handled");
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241 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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242 if (I == MBB.end())
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243 return 0;
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244
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245 if (!isUncondBranchOpcode(I->getOpcode()) &&
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246 !isCondBranchOpcode(I->getOpcode()))
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247 return 0;
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248
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249 // Remove the branch.
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250 I->eraseFromParent();
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251
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252 I = MBB.end();
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253
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254 if (I == MBB.begin())
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255 return 1;
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256 --I;
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257 if (!isCondBranchOpcode(I->getOpcode()))
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258 return 1;
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259
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260 // Remove the branch.
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261 I->eraseFromParent();
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262 return 2;
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263 }
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264
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265 void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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266 MachineBasicBlock::iterator I,
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267 const DebugLoc &dl, unsigned DestReg,
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268 unsigned SrcReg, bool KillSrc) const {
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269 assert(ARC::GPR32RegClass.contains(SrcReg) &&
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270 "Only GPR32 src copy supported.");
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271 assert(ARC::GPR32RegClass.contains(DestReg) &&
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272 "Only GPR32 dest copy supported.");
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273 BuildMI(MBB, I, dl, get(ARC::MOV_rr), DestReg)
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274 .addReg(SrcReg, getKillRegState(KillSrc));
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275 }
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276
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277 void ARCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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278 MachineBasicBlock::iterator I,
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279 unsigned SrcReg, bool isKill,
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280 int FrameIndex,
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281 const TargetRegisterClass *RC,
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282 const TargetRegisterInfo *TRI) const {
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283 DebugLoc dl = MBB.findDebugLoc(I);
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284 MachineFunction &MF = *MBB.getParent();
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285 MachineFrameInfo &MFI = MF.getFrameInfo();
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286 unsigned Align = MFI.getObjectAlignment(FrameIndex);
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287
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288 MachineMemOperand *MMO = MF.getMachineMemOperand(
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289 MachinePointerInfo::getFixedStack(MF, FrameIndex),
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290 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex), Align);
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291
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292 assert(MMO && "Couldn't get MachineMemOperand for store to stack.");
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293 assert(TRI->getSpillSize(*RC) == 4 &&
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294 "Only support 4-byte stores to stack now.");
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295 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
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296 "Only support GPR32 stores to stack now.");
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297 DEBUG(dbgs() << "Created store reg=" << PrintReg(SrcReg, TRI)
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298 << " to FrameIndex=" << FrameIndex << "\n");
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299 BuildMI(MBB, I, dl, get(ARC::ST_rs9))
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300 .addReg(SrcReg, getKillRegState(isKill))
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301 .addFrameIndex(FrameIndex)
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302 .addImm(0)
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303 .addMemOperand(MMO);
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304 }
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305
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306 void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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307 MachineBasicBlock::iterator I,
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308 unsigned DestReg, int FrameIndex,
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309 const TargetRegisterClass *RC,
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310 const TargetRegisterInfo *TRI) const {
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311 DebugLoc dl = MBB.findDebugLoc(I);
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312 MachineFunction &MF = *MBB.getParent();
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313 MachineFrameInfo &MFI = MF.getFrameInfo();
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314 unsigned Align = MFI.getObjectAlignment(FrameIndex);
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315 MachineMemOperand *MMO = MF.getMachineMemOperand(
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316 MachinePointerInfo::getFixedStack(MF, FrameIndex),
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317 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), Align);
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318
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319 assert(MMO && "Couldn't get MachineMemOperand for store to stack.");
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320 assert(TRI->getSpillSize(*RC) == 4 &&
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321 "Only support 4-byte loads from stack now.");
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322 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
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323 "Only support GPR32 stores to stack now.");
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324 DEBUG(dbgs() << "Created load reg=" << PrintReg(DestReg, TRI)
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325 << " from FrameIndex=" << FrameIndex << "\n");
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326 BuildMI(MBB, I, dl, get(ARC::LD_rs9))
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327 .addReg(DestReg, RegState::Define)
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328 .addFrameIndex(FrameIndex)
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329 .addImm(0)
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330 .addMemOperand(MMO);
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331 }
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332
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333 /// Return the inverse opcode of the specified Branch instruction.
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334 bool ARCInstrInfo::reverseBranchCondition(
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335 SmallVectorImpl<MachineOperand> &Cond) const {
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336 assert((Cond.size() == 3) && "Invalid ARC branch condition!");
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337 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm()));
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338 return false;
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339 }
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340
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341 MachineBasicBlock::iterator
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342 ARCInstrInfo::loadImmediate(MachineBasicBlock &MBB,
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343 MachineBasicBlock::iterator MI, unsigned Reg,
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344 uint64_t Value) const {
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345 DebugLoc dl = MBB.findDebugLoc(MI);
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346 if (isInt<12>(Value)) {
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347 return BuildMI(MBB, MI, dl, get(ARC::MOV_rs12), Reg)
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348 .addImm(Value)
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349 .getInstr();
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350 }
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351 llvm_unreachable("Need Arc long immediate instructions.");
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352 }
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353
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354 unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
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355 MachineBasicBlock *TBB,
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356 MachineBasicBlock *FBB,
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357 ArrayRef<MachineOperand> Cond,
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358 const DebugLoc &dl, int *BytesAdded) const {
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359 assert(!BytesAdded && "Code size not handled.");
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360
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361 // Shouldn't be a fall through.
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362 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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363 assert((Cond.size() == 3 || Cond.size() == 0) &&
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364 "ARC branch conditions have two components!");
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365
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366 if (Cond.empty()) {
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367 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(TBB);
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368 return 1;
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369 }
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370 int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p;
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371 MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(BccOpc));
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372 MIB.addMBB(TBB);
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373 for (unsigned i = 0; i < 3; i++) {
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374 MIB.add(Cond[i]);
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375 }
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376
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377 // One-way conditional branch.
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378 if (!FBB) {
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379 return 1;
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380 }
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381
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382 // Two-way conditional branch.
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383 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(FBB);
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384 return 2;
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385 }
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386
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387 unsigned ARCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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388 if (MI.getOpcode() == TargetOpcode::INLINEASM) {
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389 const MachineFunction *MF = MI.getParent()->getParent();
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390 const char *AsmStr = MI.getOperand(0).getSymbolName();
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391 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
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392 }
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393 return MI.getDesc().getSize();
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394 }
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