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1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 // License. See LICENSE.TXT for details.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 // selection DAG.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14
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77
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15 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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16 #define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
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17
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18 #include "NVPTX.h"
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19 #include "llvm/CodeGen/SelectionDAG.h"
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 #include "llvm/Target/TargetLowering.h"
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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22 namespace llvm {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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23 namespace NVPTXISD {
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95
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24 enum NodeType : unsigned {
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25 // Start the numbering from where ISD NodeType finishes.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
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27 Wrapper,
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28 CALL,
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29 RET_FLAG,
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30 LOAD_PARAM,
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31 DeclareParam,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 DeclareScalarParam,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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33 DeclareRetParam,
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34 DeclareRet,
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35 DeclareScalarRet,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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36 PrintCall,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37 PrintCallUni,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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38 CallArgBegin,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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39 CallArg,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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40 LastCallArg,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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41 CallArgEnd,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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42 CallVoid,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43 CallVal,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 CallSymbol,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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45 Prototype,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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46 MoveParam,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 PseudoUseParam,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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48 RETURN,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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49 CallSeqBegin,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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50 CallSeqEnd,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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51 CallPrototype,
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77
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52 FUN_SHFL_CLAMP,
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53 FUN_SHFR_CLAMP,
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54 MUL_WIDE_SIGNED,
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55 MUL_WIDE_UNSIGNED,
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56 IMAD,
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57 Dummy,
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58
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59 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
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60 LoadV4,
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61 LDGV2, // LDG.v2
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62 LDGV4, // LDG.v4
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63 LDUV2, // LDU.v2
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64 LDUV4, // LDU.v4
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65 StoreV2,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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66 StoreV4,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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67 LoadParam,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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68 LoadParamV2,
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69 LoadParamV4,
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70 StoreParam,
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71 StoreParamV2,
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72 StoreParamV4,
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73 StoreParamS32, // to sext and store a <32bit value, not used currently
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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74 StoreParamU32, // to zext and store a <32bit value, not used currently
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75 StoreRetval,
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76 StoreRetvalV2,
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77
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77 StoreRetvalV4,
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78
|
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79 // Texture intrinsics
|
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80 Tex1DFloatS32,
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81 Tex1DFloatFloat,
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82 Tex1DFloatFloatLevel,
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83 Tex1DFloatFloatGrad,
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84 Tex1DS32S32,
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85 Tex1DS32Float,
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86 Tex1DS32FloatLevel,
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87 Tex1DS32FloatGrad,
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88 Tex1DU32S32,
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89 Tex1DU32Float,
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90 Tex1DU32FloatLevel,
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91 Tex1DU32FloatGrad,
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92 Tex1DArrayFloatS32,
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93 Tex1DArrayFloatFloat,
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94 Tex1DArrayFloatFloatLevel,
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95 Tex1DArrayFloatFloatGrad,
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96 Tex1DArrayS32S32,
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97 Tex1DArrayS32Float,
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98 Tex1DArrayS32FloatLevel,
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99 Tex1DArrayS32FloatGrad,
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100 Tex1DArrayU32S32,
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101 Tex1DArrayU32Float,
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102 Tex1DArrayU32FloatLevel,
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103 Tex1DArrayU32FloatGrad,
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104 Tex2DFloatS32,
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105 Tex2DFloatFloat,
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106 Tex2DFloatFloatLevel,
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107 Tex2DFloatFloatGrad,
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108 Tex2DS32S32,
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109 Tex2DS32Float,
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110 Tex2DS32FloatLevel,
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111 Tex2DS32FloatGrad,
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112 Tex2DU32S32,
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113 Tex2DU32Float,
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114 Tex2DU32FloatLevel,
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115 Tex2DU32FloatGrad,
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116 Tex2DArrayFloatS32,
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117 Tex2DArrayFloatFloat,
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118 Tex2DArrayFloatFloatLevel,
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119 Tex2DArrayFloatFloatGrad,
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120 Tex2DArrayS32S32,
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121 Tex2DArrayS32Float,
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122 Tex2DArrayS32FloatLevel,
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123 Tex2DArrayS32FloatGrad,
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124 Tex2DArrayU32S32,
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125 Tex2DArrayU32Float,
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126 Tex2DArrayU32FloatLevel,
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127 Tex2DArrayU32FloatGrad,
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128 Tex3DFloatS32,
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129 Tex3DFloatFloat,
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130 Tex3DFloatFloatLevel,
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131 Tex3DFloatFloatGrad,
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132 Tex3DS32S32,
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133 Tex3DS32Float,
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134 Tex3DS32FloatLevel,
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135 Tex3DS32FloatGrad,
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136 Tex3DU32S32,
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137 Tex3DU32Float,
|
|
138 Tex3DU32FloatLevel,
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139 Tex3DU32FloatGrad,
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|
140 TexCubeFloatFloat,
|
|
141 TexCubeFloatFloatLevel,
|
|
142 TexCubeS32Float,
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|
143 TexCubeS32FloatLevel,
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|
144 TexCubeU32Float,
|
|
145 TexCubeU32FloatLevel,
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|
146 TexCubeArrayFloatFloat,
|
|
147 TexCubeArrayFloatFloatLevel,
|
|
148 TexCubeArrayS32Float,
|
|
149 TexCubeArrayS32FloatLevel,
|
|
150 TexCubeArrayU32Float,
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|
151 TexCubeArrayU32FloatLevel,
|
|
152 Tld4R2DFloatFloat,
|
|
153 Tld4G2DFloatFloat,
|
|
154 Tld4B2DFloatFloat,
|
|
155 Tld4A2DFloatFloat,
|
|
156 Tld4R2DS64Float,
|
|
157 Tld4G2DS64Float,
|
|
158 Tld4B2DS64Float,
|
|
159 Tld4A2DS64Float,
|
|
160 Tld4R2DU64Float,
|
|
161 Tld4G2DU64Float,
|
|
162 Tld4B2DU64Float,
|
|
163 Tld4A2DU64Float,
|
|
164 TexUnified1DFloatS32,
|
|
165 TexUnified1DFloatFloat,
|
|
166 TexUnified1DFloatFloatLevel,
|
|
167 TexUnified1DFloatFloatGrad,
|
|
168 TexUnified1DS32S32,
|
|
169 TexUnified1DS32Float,
|
|
170 TexUnified1DS32FloatLevel,
|
|
171 TexUnified1DS32FloatGrad,
|
|
172 TexUnified1DU32S32,
|
|
173 TexUnified1DU32Float,
|
|
174 TexUnified1DU32FloatLevel,
|
|
175 TexUnified1DU32FloatGrad,
|
|
176 TexUnified1DArrayFloatS32,
|
|
177 TexUnified1DArrayFloatFloat,
|
|
178 TexUnified1DArrayFloatFloatLevel,
|
|
179 TexUnified1DArrayFloatFloatGrad,
|
|
180 TexUnified1DArrayS32S32,
|
|
181 TexUnified1DArrayS32Float,
|
|
182 TexUnified1DArrayS32FloatLevel,
|
|
183 TexUnified1DArrayS32FloatGrad,
|
|
184 TexUnified1DArrayU32S32,
|
|
185 TexUnified1DArrayU32Float,
|
|
186 TexUnified1DArrayU32FloatLevel,
|
|
187 TexUnified1DArrayU32FloatGrad,
|
|
188 TexUnified2DFloatS32,
|
|
189 TexUnified2DFloatFloat,
|
|
190 TexUnified2DFloatFloatLevel,
|
|
191 TexUnified2DFloatFloatGrad,
|
|
192 TexUnified2DS32S32,
|
|
193 TexUnified2DS32Float,
|
|
194 TexUnified2DS32FloatLevel,
|
|
195 TexUnified2DS32FloatGrad,
|
|
196 TexUnified2DU32S32,
|
|
197 TexUnified2DU32Float,
|
|
198 TexUnified2DU32FloatLevel,
|
|
199 TexUnified2DU32FloatGrad,
|
|
200 TexUnified2DArrayFloatS32,
|
|
201 TexUnified2DArrayFloatFloat,
|
|
202 TexUnified2DArrayFloatFloatLevel,
|
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203 TexUnified2DArrayFloatFloatGrad,
|
|
204 TexUnified2DArrayS32S32,
|
|
205 TexUnified2DArrayS32Float,
|
|
206 TexUnified2DArrayS32FloatLevel,
|
|
207 TexUnified2DArrayS32FloatGrad,
|
|
208 TexUnified2DArrayU32S32,
|
|
209 TexUnified2DArrayU32Float,
|
|
210 TexUnified2DArrayU32FloatLevel,
|
|
211 TexUnified2DArrayU32FloatGrad,
|
|
212 TexUnified3DFloatS32,
|
|
213 TexUnified3DFloatFloat,
|
|
214 TexUnified3DFloatFloatLevel,
|
|
215 TexUnified3DFloatFloatGrad,
|
|
216 TexUnified3DS32S32,
|
|
217 TexUnified3DS32Float,
|
|
218 TexUnified3DS32FloatLevel,
|
|
219 TexUnified3DS32FloatGrad,
|
|
220 TexUnified3DU32S32,
|
|
221 TexUnified3DU32Float,
|
|
222 TexUnified3DU32FloatLevel,
|
|
223 TexUnified3DU32FloatGrad,
|
|
224 TexUnifiedCubeFloatFloat,
|
|
225 TexUnifiedCubeFloatFloatLevel,
|
|
226 TexUnifiedCubeS32Float,
|
|
227 TexUnifiedCubeS32FloatLevel,
|
|
228 TexUnifiedCubeU32Float,
|
|
229 TexUnifiedCubeU32FloatLevel,
|
|
230 TexUnifiedCubeArrayFloatFloat,
|
|
231 TexUnifiedCubeArrayFloatFloatLevel,
|
|
232 TexUnifiedCubeArrayS32Float,
|
|
233 TexUnifiedCubeArrayS32FloatLevel,
|
|
234 TexUnifiedCubeArrayU32Float,
|
|
235 TexUnifiedCubeArrayU32FloatLevel,
|
|
236 Tld4UnifiedR2DFloatFloat,
|
|
237 Tld4UnifiedG2DFloatFloat,
|
|
238 Tld4UnifiedB2DFloatFloat,
|
|
239 Tld4UnifiedA2DFloatFloat,
|
|
240 Tld4UnifiedR2DS64Float,
|
|
241 Tld4UnifiedG2DS64Float,
|
|
242 Tld4UnifiedB2DS64Float,
|
|
243 Tld4UnifiedA2DS64Float,
|
|
244 Tld4UnifiedR2DU64Float,
|
|
245 Tld4UnifiedG2DU64Float,
|
|
246 Tld4UnifiedB2DU64Float,
|
|
247 Tld4UnifiedA2DU64Float,
|
|
248
|
|
249 // Surface intrinsics
|
|
250 Suld1DI8Clamp,
|
|
251 Suld1DI16Clamp,
|
|
252 Suld1DI32Clamp,
|
|
253 Suld1DI64Clamp,
|
|
254 Suld1DV2I8Clamp,
|
|
255 Suld1DV2I16Clamp,
|
|
256 Suld1DV2I32Clamp,
|
|
257 Suld1DV2I64Clamp,
|
|
258 Suld1DV4I8Clamp,
|
|
259 Suld1DV4I16Clamp,
|
|
260 Suld1DV4I32Clamp,
|
|
261
|
|
262 Suld1DArrayI8Clamp,
|
|
263 Suld1DArrayI16Clamp,
|
|
264 Suld1DArrayI32Clamp,
|
|
265 Suld1DArrayI64Clamp,
|
|
266 Suld1DArrayV2I8Clamp,
|
|
267 Suld1DArrayV2I16Clamp,
|
|
268 Suld1DArrayV2I32Clamp,
|
|
269 Suld1DArrayV2I64Clamp,
|
|
270 Suld1DArrayV4I8Clamp,
|
|
271 Suld1DArrayV4I16Clamp,
|
|
272 Suld1DArrayV4I32Clamp,
|
|
273
|
|
274 Suld2DI8Clamp,
|
|
275 Suld2DI16Clamp,
|
|
276 Suld2DI32Clamp,
|
|
277 Suld2DI64Clamp,
|
|
278 Suld2DV2I8Clamp,
|
|
279 Suld2DV2I16Clamp,
|
|
280 Suld2DV2I32Clamp,
|
|
281 Suld2DV2I64Clamp,
|
|
282 Suld2DV4I8Clamp,
|
|
283 Suld2DV4I16Clamp,
|
|
284 Suld2DV4I32Clamp,
|
|
285
|
|
286 Suld2DArrayI8Clamp,
|
|
287 Suld2DArrayI16Clamp,
|
|
288 Suld2DArrayI32Clamp,
|
|
289 Suld2DArrayI64Clamp,
|
|
290 Suld2DArrayV2I8Clamp,
|
|
291 Suld2DArrayV2I16Clamp,
|
|
292 Suld2DArrayV2I32Clamp,
|
|
293 Suld2DArrayV2I64Clamp,
|
|
294 Suld2DArrayV4I8Clamp,
|
|
295 Suld2DArrayV4I16Clamp,
|
|
296 Suld2DArrayV4I32Clamp,
|
|
297
|
|
298 Suld3DI8Clamp,
|
|
299 Suld3DI16Clamp,
|
|
300 Suld3DI32Clamp,
|
|
301 Suld3DI64Clamp,
|
|
302 Suld3DV2I8Clamp,
|
|
303 Suld3DV2I16Clamp,
|
|
304 Suld3DV2I32Clamp,
|
|
305 Suld3DV2I64Clamp,
|
|
306 Suld3DV4I8Clamp,
|
|
307 Suld3DV4I16Clamp,
|
|
308 Suld3DV4I32Clamp,
|
|
309
|
|
310 Suld1DI8Trap,
|
|
311 Suld1DI16Trap,
|
|
312 Suld1DI32Trap,
|
|
313 Suld1DI64Trap,
|
|
314 Suld1DV2I8Trap,
|
|
315 Suld1DV2I16Trap,
|
|
316 Suld1DV2I32Trap,
|
|
317 Suld1DV2I64Trap,
|
|
318 Suld1DV4I8Trap,
|
|
319 Suld1DV4I16Trap,
|
|
320 Suld1DV4I32Trap,
|
|
321
|
|
322 Suld1DArrayI8Trap,
|
|
323 Suld1DArrayI16Trap,
|
|
324 Suld1DArrayI32Trap,
|
|
325 Suld1DArrayI64Trap,
|
|
326 Suld1DArrayV2I8Trap,
|
|
327 Suld1DArrayV2I16Trap,
|
|
328 Suld1DArrayV2I32Trap,
|
|
329 Suld1DArrayV2I64Trap,
|
|
330 Suld1DArrayV4I8Trap,
|
|
331 Suld1DArrayV4I16Trap,
|
|
332 Suld1DArrayV4I32Trap,
|
|
333
|
|
334 Suld2DI8Trap,
|
|
335 Suld2DI16Trap,
|
|
336 Suld2DI32Trap,
|
|
337 Suld2DI64Trap,
|
|
338 Suld2DV2I8Trap,
|
|
339 Suld2DV2I16Trap,
|
|
340 Suld2DV2I32Trap,
|
|
341 Suld2DV2I64Trap,
|
|
342 Suld2DV4I8Trap,
|
|
343 Suld2DV4I16Trap,
|
|
344 Suld2DV4I32Trap,
|
|
345
|
|
346 Suld2DArrayI8Trap,
|
|
347 Suld2DArrayI16Trap,
|
|
348 Suld2DArrayI32Trap,
|
|
349 Suld2DArrayI64Trap,
|
|
350 Suld2DArrayV2I8Trap,
|
|
351 Suld2DArrayV2I16Trap,
|
|
352 Suld2DArrayV2I32Trap,
|
|
353 Suld2DArrayV2I64Trap,
|
|
354 Suld2DArrayV4I8Trap,
|
|
355 Suld2DArrayV4I16Trap,
|
|
356 Suld2DArrayV4I32Trap,
|
|
357
|
|
358 Suld3DI8Trap,
|
|
359 Suld3DI16Trap,
|
|
360 Suld3DI32Trap,
|
|
361 Suld3DI64Trap,
|
|
362 Suld3DV2I8Trap,
|
|
363 Suld3DV2I16Trap,
|
|
364 Suld3DV2I32Trap,
|
|
365 Suld3DV2I64Trap,
|
|
366 Suld3DV4I8Trap,
|
|
367 Suld3DV4I16Trap,
|
|
368 Suld3DV4I32Trap,
|
|
369
|
|
370 Suld1DI8Zero,
|
|
371 Suld1DI16Zero,
|
|
372 Suld1DI32Zero,
|
|
373 Suld1DI64Zero,
|
|
374 Suld1DV2I8Zero,
|
|
375 Suld1DV2I16Zero,
|
|
376 Suld1DV2I32Zero,
|
|
377 Suld1DV2I64Zero,
|
|
378 Suld1DV4I8Zero,
|
|
379 Suld1DV4I16Zero,
|
|
380 Suld1DV4I32Zero,
|
|
381
|
|
382 Suld1DArrayI8Zero,
|
|
383 Suld1DArrayI16Zero,
|
|
384 Suld1DArrayI32Zero,
|
|
385 Suld1DArrayI64Zero,
|
|
386 Suld1DArrayV2I8Zero,
|
|
387 Suld1DArrayV2I16Zero,
|
|
388 Suld1DArrayV2I32Zero,
|
|
389 Suld1DArrayV2I64Zero,
|
|
390 Suld1DArrayV4I8Zero,
|
|
391 Suld1DArrayV4I16Zero,
|
|
392 Suld1DArrayV4I32Zero,
|
|
393
|
|
394 Suld2DI8Zero,
|
|
395 Suld2DI16Zero,
|
|
396 Suld2DI32Zero,
|
|
397 Suld2DI64Zero,
|
|
398 Suld2DV2I8Zero,
|
|
399 Suld2DV2I16Zero,
|
|
400 Suld2DV2I32Zero,
|
|
401 Suld2DV2I64Zero,
|
|
402 Suld2DV4I8Zero,
|
|
403 Suld2DV4I16Zero,
|
|
404 Suld2DV4I32Zero,
|
|
405
|
|
406 Suld2DArrayI8Zero,
|
|
407 Suld2DArrayI16Zero,
|
|
408 Suld2DArrayI32Zero,
|
|
409 Suld2DArrayI64Zero,
|
|
410 Suld2DArrayV2I8Zero,
|
|
411 Suld2DArrayV2I16Zero,
|
|
412 Suld2DArrayV2I32Zero,
|
|
413 Suld2DArrayV2I64Zero,
|
|
414 Suld2DArrayV4I8Zero,
|
|
415 Suld2DArrayV4I16Zero,
|
|
416 Suld2DArrayV4I32Zero,
|
|
417
|
|
418 Suld3DI8Zero,
|
|
419 Suld3DI16Zero,
|
|
420 Suld3DI32Zero,
|
|
421 Suld3DI64Zero,
|
|
422 Suld3DV2I8Zero,
|
|
423 Suld3DV2I16Zero,
|
|
424 Suld3DV2I32Zero,
|
|
425 Suld3DV2I64Zero,
|
|
426 Suld3DV4I8Zero,
|
|
427 Suld3DV4I16Zero,
|
|
428 Suld3DV4I32Zero
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
429 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
431
|
77
|
432 class NVPTXSubtarget;
|
|
433
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
434 //===--------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435 // TargetLowering Implementation
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436 //===--------------------------------------------------------------------===//
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
437 class NVPTXTargetLowering : public TargetLowering {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
438 public:
|
83
|
439 explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
|
|
440 const NVPTXSubtarget &STI);
|
77
|
441 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
442
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
443 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
444 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
445 SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
446
|
77
|
447 const char *getTargetNodeName(unsigned Opcode) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
448
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
449 bool isTypeSupportedInIntrinsic(MVT VT) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
450
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
451 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
|
77
|
452 unsigned Intrinsic) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
453
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
454 /// isLegalAddressingMode - Return true if the addressing mode represented
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
455 /// by AM is legal for this target, for a load/store of the specified type
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
456 /// Used to guide target specific optimizations, like loop strength
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
457 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
458 /// address mode (CodeGenPrepare.cpp)
|
95
|
459 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
|
|
460 unsigned AS) const override;
|
|
461
|
|
462 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
|
|
463 // Truncating 64-bit to 32-bit is free in SASS.
|
|
464 if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
|
|
465 return false;
|
|
466 return SrcTy->getPrimitiveSizeInBits() == 64 &&
|
|
467 DstTy->getPrimitiveSizeInBits() == 32;
|
|
468 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470 /// getFunctionAlignment - Return the Log2 alignment of this function.
|
77
|
471 unsigned getFunctionAlignment(const Function *F) const;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
472
|
95
|
473 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
|
|
474 EVT VT) const override {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
475 if (VT.isVector())
|
77
|
476 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
477 return MVT::i1;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
478 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
479
|
95
|
480 ConstraintType getConstraintType(StringRef Constraint) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
481 std::pair<unsigned, const TargetRegisterClass *>
|
95
|
482 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
|
483 StringRef Constraint, MVT VT) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
484
|
77
|
485 SDValue LowerFormalArguments(
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
486 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
487 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
|
77
|
488 SmallVectorImpl<SDValue> &InVals) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
489
|
77
|
490 SDValue LowerCall(CallLoweringInfo &CLI,
|
|
491 SmallVectorImpl<SDValue> &InVals) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
492
|
95
|
493 std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
494 const SmallVectorImpl<ISD::OutputArg> &,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
495 unsigned retAlignment,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
496 const ImmutableCallSite *CS) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
497
|
77
|
498 SDValue
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
499 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
500 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
501 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
|
77
|
502 SelectionDAG &DAG) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
503
|
77
|
504 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
|
|
505 std::vector<SDValue> &Ops,
|
|
506 SelectionDAG &DAG) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
507
|
77
|
508 const NVPTXTargetMachine *nvTM;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
509
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
510 // PTX always uses 32-bit shift amounts
|
95
|
511 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
|
|
512 return MVT::i32;
|
|
513 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
514
|
77
|
515 TargetLoweringBase::LegalizeTypeAction
|
|
516 getPreferredVectorAction(EVT VT) const override;
|
|
517
|
|
518 bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
|
|
519
|
|
520 bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
521
|
83
|
522 bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
|
|
523
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
524 private:
|
83
|
525 const NVPTXSubtarget &STI; // cache the subtarget here
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
527 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
528 EVT = MVT::i32) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
529 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
530 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
531
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
532 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
533
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
534 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
535 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
536
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
537 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
538 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
539 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
540
|
77
|
541 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
|
|
542 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
|
|
543
|
83
|
544 SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
|
|
545
|
77
|
546 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
|
|
547 SelectionDAG &DAG) const override;
|
|
548 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
549
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
550 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
551 Type *Ty, unsigned Idx) const;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
552 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
553 } // namespace llvm
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
554
|
77
|
555 #endif
|