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1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // Top-level implementation for the NVPTX target.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "NVPTXTargetMachine.h"
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15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
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16 #include "NVPTX.h"
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17 #include "NVPTXAllocaHoisting.h"
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18 #include "NVPTXLowerAggrCopies.h"
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83
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19 #include "NVPTXTargetObjectFile.h"
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|
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20 #include "NVPTXTargetTransformInfo.h"
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21 #include "llvm/Analysis/Passes.h"
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22 #include "llvm/CodeGen/AsmPrinter.h"
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23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
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24 #include "llvm/CodeGen/MachineModuleInfo.h"
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25 #include "llvm/CodeGen/Passes.h"
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26 #include "llvm/IR/DataLayout.h"
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77
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27 #include "llvm/IR/IRPrintingPasses.h"
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83
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28 #include "llvm/IR/LegacyPassManager.h"
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77
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29 #include "llvm/IR/Verifier.h"
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30 #include "llvm/MC/MCAsmInfo.h"
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31 #include "llvm/MC/MCInstrInfo.h"
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32 #include "llvm/MC/MCStreamer.h"
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33 #include "llvm/MC/MCSubtargetInfo.h"
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34 #include "llvm/Support/CommandLine.h"
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35 #include "llvm/Support/Debug.h"
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36 #include "llvm/Support/FormattedStream.h"
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37 #include "llvm/Support/TargetRegistry.h"
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38 #include "llvm/Support/raw_ostream.h"
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39 #include "llvm/Target/TargetInstrInfo.h"
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40 #include "llvm/Target/TargetLowering.h"
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41 #include "llvm/Target/TargetLoweringObjectFile.h"
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42 #include "llvm/Target/TargetMachine.h"
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43 #include "llvm/Target/TargetOptions.h"
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44 #include "llvm/Target/TargetRegisterInfo.h"
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45 #include "llvm/Target/TargetSubtargetInfo.h"
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46 #include "llvm/Transforms/Scalar.h"
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47
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48 using namespace llvm;
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49
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50 namespace llvm {
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51 void initializeNVVMReflectPass(PassRegistry&);
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52 void initializeGenericToNVVMPass(PassRegistry&);
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95
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53 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
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77
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54 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
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55 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
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95
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56 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
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57 void initializeNVPTXLowerKernelArgsPass(PassRegistry &);
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58 void initializeNVPTXLowerAllocaPass(PassRegistry &);
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59 }
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60
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61 extern "C" void LLVMInitializeNVPTXTarget() {
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62 // Register the target.
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63 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
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64 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
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65
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66 // FIXME: This pass is really intended to be invoked during IR optimization,
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67 // but it's very NVPTX-specific.
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68 PassRegistry &PR = *PassRegistry::getPassRegistry();
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69 initializeNVVMReflectPass(PR);
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70 initializeGenericToNVVMPass(PR);
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71 initializeNVPTXAllocaHoistingPass(PR);
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72 initializeNVPTXAssignValidGlobalNamesPass(PR);
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73 initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
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74 initializeNVPTXLowerKernelArgsPass(PR);
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75 initializeNVPTXLowerAllocaPass(PR);
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76 initializeNVPTXLowerAggrCopiesPass(PR);
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83
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77 }
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78
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79 static std::string computeDataLayout(bool is64Bit) {
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80 std::string Ret = "e";
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81
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82 if (!is64Bit)
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83 Ret += "-p:32:32";
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84
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85 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
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86
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87 return Ret;
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88 }
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89
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95
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90 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
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77
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91 StringRef CPU, StringRef FS,
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92 const TargetOptions &Options,
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93 Reloc::Model RM, CodeModel::Model CM,
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94 CodeGenOpt::Level OL, bool is64bit)
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95
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95 : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
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96 CM, OL),
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97 is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
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98 Subtarget(TT, CPU, FS, *this) {
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99 if (TT.getOS() == Triple::NVCL)
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100 drvInterface = NVPTX::NVCL;
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101 else
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102 drvInterface = NVPTX::CUDA;
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103 initAsmInfo();
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104 }
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105
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106 NVPTXTargetMachine::~NVPTXTargetMachine() {}
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107
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108 void NVPTXTargetMachine32::anchor() {}
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109
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110 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
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111 StringRef CPU, StringRef FS,
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112 const TargetOptions &Options,
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113 Reloc::Model RM, CodeModel::Model CM,
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114 CodeGenOpt::Level OL)
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115 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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116
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117 void NVPTXTargetMachine64::anchor() {}
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118
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119 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
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120 StringRef CPU, StringRef FS,
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121 const TargetOptions &Options,
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122 Reloc::Model RM, CodeModel::Model CM,
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123 CodeGenOpt::Level OL)
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124 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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125
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126 namespace {
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127 class NVPTXPassConfig : public TargetPassConfig {
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128 public:
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129 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
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130 : TargetPassConfig(TM, PM) {}
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131
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132 NVPTXTargetMachine &getNVPTXTargetMachine() const {
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133 return getTM<NVPTXTargetMachine>();
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134 }
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135
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136 void addIRPasses() override;
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137 bool addInstSelector() override;
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83
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138 void addPostRegAlloc() override;
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77
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139 void addMachineSSAOptimization() override;
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140
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77
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141 FunctionPass *createTargetRegisterAllocator(bool) override;
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142 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
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143 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
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95
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144
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145 private:
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146 // if the opt level is aggressive, add GVN; otherwise, add EarlyCSE.
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147 void addEarlyCSEOrGVNPass();
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148 };
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149 } // end anonymous namespace
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150
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151 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
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152 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
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153 return PassConfig;
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154 }
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155
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156 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
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95
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157 return TargetIRAnalysis([this](const Function &F) {
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158 return TargetTransformInfo(NVPTXTTIImpl(this, F));
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159 });
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160 }
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161
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162 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
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163 if (getOptLevel() == CodeGenOpt::Aggressive)
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164 addPass(createGVNPass());
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165 else
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166 addPass(createEarlyCSEPass());
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83
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167 }
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168
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169 void NVPTXPassConfig::addIRPasses() {
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170 // The following passes are known to not play well with virtual regs hanging
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171 // around after register allocation (which in our case, is *all* registers).
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172 // We explicitly disable them here. We do, however, need some functionality
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173 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
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174 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
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175 disablePass(&PrologEpilogCodeInserterID);
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176 disablePass(&MachineCopyPropagationID);
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177 disablePass(&TailDuplicateID);
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178
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179 addPass(createNVVMReflectPass());
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77
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180 addPass(createNVPTXImageOptimizerPass());
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181 addPass(createNVPTXAssignValidGlobalNamesPass());
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182 addPass(createGenericToNVVMPass());
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95
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183
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184 // === Propagate special address spaces ===
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185 addPass(createNVPTXLowerKernelArgsPass(&getNVPTXTargetMachine()));
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186 // NVPTXLowerKernelArgs emits alloca for byval parameters which can often
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187 // be eliminated by SROA.
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188 addPass(createSROAPass());
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189 addPass(createNVPTXLowerAllocaPass());
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77
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190 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
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95
|
191 // FavorNonGenericAddrSpaces shortcuts unnecessary addrspacecasts, and leave
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192 // them unused. We could remove dead code in an ad-hoc manner, but that
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193 // requires manual work and might be error-prone.
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194 addPass(createDeadCodeEliminationPass());
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195
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196 // === Straight-line scalar optimizations ===
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77
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197 addPass(createSeparateConstOffsetFromGEPPass());
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95
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198 addPass(createSpeculativeExecutionPass());
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199 // ReassociateGEPs exposes more opportunites for SLSR. See
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200 // the example in reassociate-geps-and-slsr.ll.
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201 addPass(createStraightLineStrengthReducePass());
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202 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
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203 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
|
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204 // for some of our benchmarks.
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205 addEarlyCSEOrGVNPass();
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206 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
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207 addPass(createNaryReassociatePass());
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208 // NaryReassociate on GEPs creates redundant common expressions, so run
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|
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209 // EarlyCSE after it.
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210 addPass(createEarlyCSEPass());
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211
|
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212 // === LSR and other generic IR passes ===
|
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213 TargetPassConfig::addIRPasses();
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214 // EarlyCSE is not always strong enough to clean up what LSR produces. For
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215 // example, GVN can combine
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77
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216 //
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95
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217 // %0 = add %a, %b
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218 // %1 = add %b, %a
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219 //
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220 // and
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221 //
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222 // %0 = shl nsw %a, 2
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223 // %1 = shl %a, 2
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224 //
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225 // but EarlyCSE can do neither of them.
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226 addEarlyCSEOrGVNPass();
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227 }
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228
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229 bool NVPTXPassConfig::addInstSelector() {
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95
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230 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
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231
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232 addPass(createLowerAggrCopies());
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233 addPass(createAllocaHoisting());
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234 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
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235
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236 if (!ST.hasImageHandles())
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237 addPass(createNVPTXReplaceImageHandlesPass());
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238
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239 return false;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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240 }
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241
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83
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242 void NVPTXPassConfig::addPostRegAlloc() {
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243 addPass(createNVPTXPrologEpilogPass(), false);
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95
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244 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
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245 // index with VRFrame register. NVPTXPeephole need to be run after that and
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246 // will replace VRFrame with VRFrameLocal when possible.
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247 addPass(createNVPTXPeephole());
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248 }
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249
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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250 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
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251 return nullptr; // No reg alloc
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252 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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253
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254 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
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255 assert(!RegAllocPass && "NVPTX uses no regalloc!");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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256 addPass(&PHIEliminationID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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257 addPass(&TwoAddressInstructionPassID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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258 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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259
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260 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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261 assert(!RegAllocPass && "NVPTX uses no regalloc!");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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262
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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263 addPass(&ProcessImplicitDefsID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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264 addPass(&LiveVariablesID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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265 addPass(&MachineLoopInfoID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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266 addPass(&PHIEliminationID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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267
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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268 addPass(&TwoAddressInstructionPassID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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269 addPass(&RegisterCoalescerID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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270
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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271 // PreRA instruction scheduling.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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272 if (addPass(&MachineSchedulerID))
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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273 printAndVerify("After Machine Scheduling");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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274
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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275
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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276 addPass(&StackSlotColoringID);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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277
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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278 // FIXME: Needs physical registers
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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279 //addPass(&PostRAMachineLICMID);
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280
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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281 printAndVerify("After StackSlotColoring");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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282 }
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77
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283
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284 void NVPTXPassConfig::addMachineSSAOptimization() {
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285 // Pre-ra tail duplication.
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286 if (addPass(&EarlyTailDuplicateID))
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287 printAndVerify("After Pre-RegAlloc TailDuplicate");
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288
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289 // Optimize PHIs before DCE: removing dead PHI cycles may make more
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290 // instructions dead.
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291 addPass(&OptimizePHIsID);
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292
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293 // This pass merges large allocas. StackSlotColoring is a different pass
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294 // which merges spill slots.
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295 addPass(&StackColoringID);
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296
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297 // If the target requests it, assign local variables to stack slots relative
|
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298 // to one another and simplify frame index references where possible.
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299 addPass(&LocalStackSlotAllocationID);
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300
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301 // With optimization, dead code should already be eliminated. However
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302 // there is one known exception: lowered code for arguments that are only
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303 // used by tail calls, where the tail calls reuse the incoming stack
|
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304 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
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305 addPass(&DeadMachineInstructionElimID);
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306 printAndVerify("After codegen DCE pass");
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307
|
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308 // Allow targets to insert passes that improve instruction level parallelism,
|
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309 // like if-conversion. Such passes will typically need dominator trees and
|
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310 // loop info, just like LICM and CSE below.
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311 if (addILPOpts())
|
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312 printAndVerify("After ILP optimizations");
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313
|
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|
314 addPass(&MachineLICMID);
|
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315 addPass(&MachineCSEID);
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316
|
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317 addPass(&MachineSinkingID);
|
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318 printAndVerify("After Machine LICM, CSE and Sinking passes");
|
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319
|
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|
320 addPass(&PeepholeOptimizerID);
|
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|
321 printAndVerify("After codegen peephole optimization pass");
|
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322 }
|
