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annotate test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/llvm.AMDGPU.rsq.clamped.f64.ll@60c9769439b8
children
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60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
60c9769439b8 LLVM 3.7
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
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54457678186b LLVM 3.6
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54457678186b LLVM 3.6
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4 declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
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6 ; FUNC-LABEL: {{^}}rsq_clamped_f64:
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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7 ; SI: v_rsq_clamp_f64_e32
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60c9769439b8 LLVM 3.7
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9 ; VI: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[2:3]
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10 ; TODO: this constant should be folded:
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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11 ; VI: s_mov_b32 s[[ALLBITS:[0-9+]]], -1
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12 ; VI: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
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13 ; VI: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]]
60c9769439b8 LLVM 3.7
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parents: 77
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14 ; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
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parents: 77
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15 ; VI: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
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parents: 77
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16 ; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]]
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parents: 77
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17 ; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
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54457678186b LLVM 3.6
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19 define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind {
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20 %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
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21 store double %rsq_clamped, double addrspace(1)* %out, align 8
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22 ret void
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23 }