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1 //===-- LanaiISelDAGToDAG.cpp - A dag to dag inst selector for Lanai ------===//
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2 //
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147
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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120
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file defines an instruction selector for the Lanai target.
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10 //
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11 //===----------------------------------------------------------------------===//
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12
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147
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13 #include "LanaiAluCode.h"
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120
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14 #include "LanaiMachineFunctionInfo.h"
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15 #include "LanaiRegisterInfo.h"
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16 #include "LanaiSubtarget.h"
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17 #include "LanaiTargetMachine.h"
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18 #include "llvm/CodeGen/MachineConstantPool.h"
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19 #include "llvm/CodeGen/MachineFrameInfo.h"
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20 #include "llvm/CodeGen/MachineFunction.h"
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21 #include "llvm/CodeGen/MachineInstrBuilder.h"
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22 #include "llvm/CodeGen/MachineRegisterInfo.h"
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23 #include "llvm/CodeGen/SelectionDAGISel.h"
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24 #include "llvm/IR/CFG.h"
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25 #include "llvm/IR/GlobalValue.h"
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26 #include "llvm/IR/Instructions.h"
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27 #include "llvm/IR/Intrinsics.h"
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28 #include "llvm/IR/Type.h"
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29 #include "llvm/Support/Debug.h"
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30 #include "llvm/Support/ErrorHandling.h"
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31 #include "llvm/Support/raw_ostream.h"
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32 #include "llvm/Target/TargetMachine.h"
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33
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34 using namespace llvm;
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35
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36 #define DEBUG_TYPE "lanai-isel"
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37
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38 //===----------------------------------------------------------------------===//
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39 // Instruction Selector Implementation
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40 //===----------------------------------------------------------------------===//
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41
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42 //===----------------------------------------------------------------------===//
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43 // LanaiDAGToDAGISel - Lanai specific code to select Lanai machine
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44 // instructions for SelectionDAG operations.
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45 //===----------------------------------------------------------------------===//
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46 namespace {
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47
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48 class LanaiDAGToDAGISel : public SelectionDAGISel {
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49 public:
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50 explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
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51 : SelectionDAGISel(TargetMachine) {}
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52
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53 bool runOnMachineFunction(MachineFunction &MF) override {
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54 return SelectionDAGISel::runOnMachineFunction(MF);
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55 }
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56
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57 // Pass Name
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58 StringRef getPassName() const override {
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59 return "Lanai DAG->DAG Pattern Instruction Selection";
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60 }
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61
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62 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
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63 std::vector<SDValue> &OutOps) override;
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64
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65 private:
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66 // Include the pieces autogenerated from the target description.
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67 #include "LanaiGenDAGISel.inc"
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68
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69 // Instruction Selection not handled by the auto-generated tablgen
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70 void Select(SDNode *N) override;
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71
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72 // Support functions for the opcodes of Instruction Selection
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73 // not handled by the auto-generated tablgen
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74 void selectFrameIndex(SDNode *N);
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75
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76 // Complex Pattern for address selection.
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77 bool selectAddrRi(SDValue Addr, SDValue &Base, SDValue &Offset,
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78 SDValue &AluOp);
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79 bool selectAddrRr(SDValue Addr, SDValue &R1, SDValue &R2, SDValue &AluOp);
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80 bool selectAddrSls(SDValue Addr, SDValue &Offset);
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81 bool selectAddrSpls(SDValue Addr, SDValue &Base, SDValue &Offset,
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82 SDValue &AluOp);
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83
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84 // getI32Imm - Return a target constant with the specified value, of type i32.
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85 inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
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86 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
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87 }
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88
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89 private:
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90 bool selectAddrRiSpls(SDValue Addr, SDValue &Base, SDValue &Offset,
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91 SDValue &AluOp, bool RiMode);
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92 };
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93
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94 bool canBeRepresentedAsSls(const ConstantSDNode &CN) {
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95 // Fits in 21-bit signed immediate and two low-order bits are zero.
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96 return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0);
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97 }
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98
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99 } // namespace
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100
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101 // Helper functions for ComplexPattern used on LanaiInstrInfo
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102 // Used on Lanai Load/Store instructions.
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103 bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
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104 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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105 SDLoc DL(Addr);
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106 // Loading from a constant address.
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107 if (canBeRepresentedAsSls(*CN)) {
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108 int32_t Imm = CN->getSExtValue();
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109 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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110 return true;
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111 }
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112 }
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113 if (Addr.getOpcode() == ISD::OR &&
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114 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) {
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115 Offset = Addr.getOperand(1).getOperand(0);
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116 return true;
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117 }
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118 return false;
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119 }
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120
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121 bool LanaiDAGToDAGISel::selectAddrRiSpls(SDValue Addr, SDValue &Base,
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122 SDValue &Offset, SDValue &AluOp,
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123 bool RiMode) {
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124 SDLoc DL(Addr);
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125
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126 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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127 if (RiMode) {
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128 // Fits in 16-bit signed immediate.
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129 if (isInt<16>(CN->getSExtValue())) {
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130 int16_t Imm = CN->getSExtValue();
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131 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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132 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
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133 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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134 return true;
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135 }
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136 // Allow SLS to match if the constant doesn't fit in 16 bits but can be
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137 // represented as an SLS.
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138 if (canBeRepresentedAsSls(*CN))
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139 return false;
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140 } else {
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141 // Fits in 10-bit signed immediate.
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142 if (isInt<10>(CN->getSExtValue())) {
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143 int16_t Imm = CN->getSExtValue();
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144 Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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145 Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
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146 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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147 return true;
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148 }
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149 }
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150 }
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151
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152 // if Address is FI, get the TargetFrameIndex.
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153 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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154 Base = CurDAG->getTargetFrameIndex(
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155 FIN->getIndex(),
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156 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
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157 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
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158 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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159 return true;
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160 }
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161
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162 // Skip direct calls
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163 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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164 Addr.getOpcode() == ISD::TargetGlobalAddress))
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165 return false;
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166
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167 // Address of the form imm + reg
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168 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
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169 if (AluOperator == ISD::ADD) {
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170 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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171 // Addresses of the form FI+const
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172 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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173 if ((RiMode && isInt<16>(CN->getSExtValue())) ||
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174 (!RiMode && isInt<10>(CN->getSExtValue()))) {
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175 // If the first operand is a FI, get the TargetFI Node
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176 if (FrameIndexSDNode *FIN =
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177 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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178 Base = CurDAG->getTargetFrameIndex(
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179 FIN->getIndex(),
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180 getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
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181 } else {
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182 Base = Addr.getOperand(0);
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183 }
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184
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185 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32);
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186 return true;
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187 }
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188 }
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189
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190 // Let SLS match SMALL instead of RI.
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191 if (AluOperator == ISD::OR && RiMode &&
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192 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
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193 return false;
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194
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195 Base = Addr;
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196 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
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197 AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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198 return true;
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199 }
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200
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201 bool LanaiDAGToDAGISel::selectAddrRi(SDValue Addr, SDValue &Base,
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202 SDValue &Offset, SDValue &AluOp) {
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203 return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/true);
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204 }
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205
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206 bool LanaiDAGToDAGISel::selectAddrSpls(SDValue Addr, SDValue &Base,
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207 SDValue &Offset, SDValue &AluOp) {
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208 return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/false);
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209 }
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210
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211 bool LanaiDAGToDAGISel::selectAddrRr(SDValue Addr, SDValue &R1, SDValue &R2,
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212 SDValue &AluOp) {
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213 // if Address is FI, get the TargetFrameIndex.
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214 if (Addr.getOpcode() == ISD::FrameIndex)
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215 return false;
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216
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217 // Skip direct calls
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218 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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219 Addr.getOpcode() == ISD::TargetGlobalAddress))
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220 return false;
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221
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222 // Address of the form OP + OP
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223 ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
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224 LPAC::AluCode AluCode = LPAC::isdToLanaiAluCode(AluOperator);
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225 if (AluCode != LPAC::UNKNOWN) {
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226 // Skip addresses of the form FI OP const
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227 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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228 if (isInt<16>(CN->getSExtValue()))
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229 return false;
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230
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231 // Skip addresses with hi/lo operands
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232 if (Addr.getOperand(0).getOpcode() == LanaiISD::HI ||
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233 Addr.getOperand(0).getOpcode() == LanaiISD::LO ||
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234 Addr.getOperand(0).getOpcode() == LanaiISD::SMALL ||
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235 Addr.getOperand(1).getOpcode() == LanaiISD::HI ||
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236 Addr.getOperand(1).getOpcode() == LanaiISD::LO ||
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237 Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
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238 return false;
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239
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240 // Addresses of the form register OP register
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241 R1 = Addr.getOperand(0);
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242 R2 = Addr.getOperand(1);
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243 AluOp = CurDAG->getTargetConstant(AluCode, SDLoc(Addr), MVT::i32);
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244 return true;
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245 }
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246
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247 // Skip addresses with zero offset
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248 return false;
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249 }
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250
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251 bool LanaiDAGToDAGISel::SelectInlineAsmMemoryOperand(
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252 const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
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253 SDValue Op0, Op1, AluOp;
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254 switch (ConstraintCode) {
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255 default:
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256 return true;
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257 case InlineAsm::Constraint_m: // memory
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258 if (!selectAddrRr(Op, Op0, Op1, AluOp) &&
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259 !selectAddrRi(Op, Op0, Op1, AluOp))
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260 return true;
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261 break;
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262 }
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263
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264 OutOps.push_back(Op0);
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265 OutOps.push_back(Op1);
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266 OutOps.push_back(AluOp);
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267 return false;
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268 }
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269
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270 // Select instructions not customized! Used for
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271 // expanded, promoted and normal instructions
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272 void LanaiDAGToDAGISel::Select(SDNode *Node) {
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273 unsigned Opcode = Node->getOpcode();
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274
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275 // If we have a custom node, we already have selected!
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276 if (Node->isMachineOpcode()) {
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147
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277 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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120
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278 return;
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279 }
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280
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121
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281 // Instruction Selection not handled by the auto-generated tablegen selection
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282 // should be handled here.
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283 EVT VT = Node->getValueType(0);
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120
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284 switch (Opcode) {
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121
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285 case ISD::Constant:
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286 if (VT == MVT::i32) {
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287 ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
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288 // Materialize zero constants as copies from R0. This allows the coalescer
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289 // to propagate these into other instructions.
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290 if (ConstNode->isNullValue()) {
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291 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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292 SDLoc(Node), Lanai::R0, MVT::i32);
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293 return ReplaceNode(Node, New.getNode());
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294 }
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295 // Materialize all ones constants as copies from R1. This allows the
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296 // coalescer to propagate these into other instructions.
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297 if (ConstNode->isAllOnesValue()) {
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298 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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299 SDLoc(Node), Lanai::R1, MVT::i32);
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300 return ReplaceNode(Node, New.getNode());
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301 }
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302 }
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303 break;
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120
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304 case ISD::FrameIndex:
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305 selectFrameIndex(Node);
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306 return;
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307 default:
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308 break;
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309 }
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310
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311 // Select the default instruction
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312 SelectCode(Node);
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313 }
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314
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315 void LanaiDAGToDAGISel::selectFrameIndex(SDNode *Node) {
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316 SDLoc DL(Node);
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317 SDValue Imm = CurDAG->getTargetConstant(0, DL, MVT::i32);
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147
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318 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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120
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319 EVT VT = Node->getValueType(0);
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320 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
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321 unsigned Opc = Lanai::ADD_I_LO;
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322 if (Node->hasOneUse()) {
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323 CurDAG->SelectNodeTo(Node, Opc, VT, TFI, Imm);
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324 return;
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325 }
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326 ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VT, TFI, Imm));
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327 }
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328
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329 // createLanaiISelDag - This pass converts a legalized DAG into a
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330 // Lanai-specific DAG, ready for instruction scheduling.
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331 FunctionPass *llvm::createLanaiISelDag(LanaiTargetMachine &TM) {
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332 return new LanaiDAGToDAGISel(TM);
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333 }
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