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147
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1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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121
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2
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3
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4 ; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
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5 ; See PR33579.
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6 ; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj %s
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7 ; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
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8
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9 ; OBJ: Relocations [
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10 ; OBJ-NEXT: ]
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11
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120
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12 ; Restrict maximum branch to between +7 and -8 dwords
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13
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14 ; Used to emit an always 4 byte instruction. Inline asm always assumes
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15 ; each instruction is the maximum size.
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16 declare void @llvm.amdgcn.s.sleep(i32) #0
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17
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18 declare i32 @llvm.amdgcn.workitem.id.x() #1
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19
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20
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21 ; GCN-LABEL: {{^}}uniform_conditional_max_short_forward_branch:
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22 ; GCN: s_load_dword [[CND:s[0-9]+]]
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23 ; GCN: s_cmp_eq_u32 [[CND]], 0
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24 ; GCN-NEXT: s_cbranch_scc1 [[BB3:BB[0-9]+_[0-9]+]]
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25
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26
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134
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27 ; GCN-NEXT: ; %bb.1: ; %bb2
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120
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28 ; GCN-NEXT: ;;#ASMSTART
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29 ; GCN-NEXT: v_nop_e64
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30 ; GCN-NEXT: v_nop_e64
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31 ; GCN-NEXT: v_nop_e64
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32 ; GCN-NEXT: ;;#ASMEND
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33 ; GCN-NEXT: s_sleep 0
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34
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35 ; GCN-NEXT: [[BB3]]: ; %bb3
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36 ; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
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37 ; GCN: buffer_store_dword [[V_CND]]
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38 ; GCN: s_endpgm
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121
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39 define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
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120
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40 bb:
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41 %cmp = icmp eq i32 %cnd, 0
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42 br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
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43
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44 bb2:
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45 ; 24 bytes
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46 call void asm sideeffect
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47 "v_nop_e64
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48 v_nop_e64
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49 v_nop_e64", ""() #0
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50 call void @llvm.amdgcn.s.sleep(i32 0)
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51 br label %bb3
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52
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53 bb3:
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54 store volatile i32 %cnd, i32 addrspace(1)* %arg
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55 ret void
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56 }
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57
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58 ; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch:
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59 ; GCN: s_load_dword [[CND:s[0-9]+]]
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60 ; GCN: s_cmp_eq_u32 [[CND]], 0
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61 ; GCN-NEXT: s_cbranch_scc0 [[LONGBB:BB[0-9]+_[0-9]+]]
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62
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63 ; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb0
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147
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64 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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65 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
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66 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
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67 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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120
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68
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69 ; GCN-NEXT: [[LONGBB]]:
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70 ; GCN-NEXT: ;;#ASMSTART
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71 ; GCN: v_nop_e64
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72 ; GCN: v_nop_e64
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73 ; GCN: v_nop_e64
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74 ; GCN: v_nop_e64
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75 ; GCN-NEXT: ;;#ASMEND
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76
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77 ; GCN-NEXT: [[ENDBB]]:
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78 ; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
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79 ; GCN: buffer_store_dword [[V_CND]]
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80 ; GCN: s_endpgm
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121
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81 define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
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120
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82 bb0:
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83 %cmp = icmp eq i32 %cnd, 0
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84 br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
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85
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86 bb2:
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87 ; 32 bytes
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88 call void asm sideeffect
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89 "v_nop_e64
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90 v_nop_e64
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91 v_nop_e64
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92 v_nop_e64", ""() #0
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93 br label %bb3
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94
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95 bb3:
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96 store volatile i32 %cnd, i32 addrspace(1)* %arg
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97 ret void
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98 }
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99
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100 ; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch:
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101 ; GCN: s_load_dword [[CND:s[0-9]+]]
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102 ; GCN-DAG: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
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134
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103 ; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0
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104 ; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]]
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120
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105 ; GCN: s_cbranch_vccz [[LONGBB:BB[0-9]+_[0-9]+]]
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106
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107 ; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb0
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147
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108 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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109 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
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110 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
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111 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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120
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112
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113 ; GCN-NEXT: [[LONGBB]]:
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114 ; GCN: v_nop_e64
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115 ; GCN: v_nop_e64
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116 ; GCN: v_nop_e64
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117 ; GCN: v_nop_e64
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118
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119 ; GCN: [[ENDBB]]:
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120 ; GCN: buffer_store_dword [[V_CND]]
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121 ; GCN: s_endpgm
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121
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122 define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(float addrspace(1)* %arg, float %cnd) #0 {
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120
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123 bb0:
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124 %cmp = fcmp oeq float %cnd, 0.0
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125 br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
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126
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127 bb2:
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128 call void asm sideeffect " ; 32 bytes
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129 v_nop_e64
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130 v_nop_e64
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131 v_nop_e64
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132 v_nop_e64", ""() #0
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133 br label %bb3
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134
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135 bb3:
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136 store volatile float %cnd, float addrspace(1)* %arg
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137 ret void
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138 }
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139
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140 ; GCN-LABEL: {{^}}min_long_forward_vbranch:
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141
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142 ; GCN: buffer_load_dword
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143 ; GCN: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
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144 ; GCN: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
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145
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146 ; GCN: v_nop_e64
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147 ; GCN: v_nop_e64
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148 ; GCN: v_nop_e64
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149 ; GCN: v_nop_e64
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150
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151 ; GCN: s_or_b64 exec, exec, [[SAVE]]
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152 ; GCN: buffer_store_dword
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153 ; GCN: s_endpgm
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121
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154 define amdgpu_kernel void @min_long_forward_vbranch(i32 addrspace(1)* %arg) #0 {
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120
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155 bb:
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156 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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157 %tid.ext = zext i32 %tid to i64
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158 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tid.ext
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159 %load = load volatile i32, i32 addrspace(1)* %gep
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160 %cmp = icmp eq i32 %load, 0
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161 br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
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162
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163 bb2:
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164 call void asm sideeffect " ; 32 bytes
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165 v_nop_e64
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166 v_nop_e64
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167 v_nop_e64
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168 v_nop_e64", ""() #0
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169 br label %bb3
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170
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171 bb3:
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172 store volatile i32 %load, i32 addrspace(1)* %gep
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173 ret void
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174 }
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175
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176 ; GCN-LABEL: {{^}}long_backward_sbranch:
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121
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177 ; GCN: s_mov_b32 [[LOOPIDX:s[0-9]+]], 0{{$}}
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120
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178
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179 ; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; %bb2
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180 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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121
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181 ; GCN-NEXT: s_add_i32 [[INC:s[0-9]+]], [[LOOPIDX]], 1
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182 ; GCN-NEXT: s_cmp_lt_i32 [[INC]], 10
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120
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183
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184 ; GCN-NEXT: ;;#ASMSTART
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185 ; GCN-NEXT: v_nop_e64
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186 ; GCN-NEXT: v_nop_e64
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187 ; GCN-NEXT: v_nop_e64
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188 ; GCN-NEXT: ;;#ASMEND
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189
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121
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190 ; GCN-NEXT: s_cbranch_scc0 [[ENDBB:BB[0-9]+_[0-9]+]]
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120
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191
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192 ; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb2
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193 ; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1
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147
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194
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195 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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196 ; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_JUMP]]+4)-[[LOOPBB]]
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197 ; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0
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198 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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120
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199
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200 ; GCN-NEXT: [[ENDBB]]:
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201 ; GCN-NEXT: s_endpgm
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121
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202 define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 {
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120
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203 bb:
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204 br label %bb2
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205
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206 bb2:
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207 %loop.idx = phi i32 [ 0, %bb ], [ %inc, %bb2 ]
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208 ; 24 bytes
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209 call void asm sideeffect
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210 "v_nop_e64
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211 v_nop_e64
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212 v_nop_e64", ""() #0
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213 %inc = add nsw i32 %loop.idx, 1 ; add cost 4
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214 %cmp = icmp slt i32 %inc, 10 ; condition cost = 8
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215 br i1 %cmp, label %bb2, label %bb3 ; -
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216
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217 bb3:
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218 ret void
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219 }
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220
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221 ; Requires expansion of unconditional branch from %bb2 to %bb4 (and
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222 ; expansion of conditional branch from %bb to %bb3.
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223
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224 ; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch:
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225 ; GCN: s_cmp_eq_u32
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226 ; GCN-NEXT: s_cbranch_scc0 [[BB2:BB[0-9]+_[0-9]+]]
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227
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228 ; GCN-NEXT: [[LONG_JUMP0:BB[0-9]+_[0-9]+]]: ; %bb0
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147
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229 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
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230 ; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], [[BB3:BB[0-9]_[0-9]+]]-([[LONG_JUMP0]]+4)
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231 ; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], 0{{$}}
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232 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}}
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120
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233
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234 ; GCN-NEXT: [[BB2]]: ; %bb2
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235 ; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17
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236 ; GCN: buffer_store_dword [[BB2_K]]
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237
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238 ; GCN-NEXT: [[LONG_JUMP1:BB[0-9]+_[0-9]+]]: ; %bb2
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147
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239 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
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240 ; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB4:BB[0-9]_[0-9]+]]-([[LONG_JUMP1]]+4)
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241 ; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}}
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242 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
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120
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243
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244 ; GCN: [[BB3]]: ; %bb3
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245 ; GCN: v_nop_e64
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246 ; GCN: v_nop_e64
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247 ; GCN: v_nop_e64
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248 ; GCN: v_nop_e64
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249 ; GCN: ;;#ASMEND
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250
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251 ; GCN-NEXT: [[BB4]]: ; %bb4
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252 ; GCN: v_mov_b32_e32 [[BB4_K:v[0-9]+]], 63
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253 ; GCN: buffer_store_dword [[BB4_K]]
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254 ; GCN-NEXT: s_endpgm
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255 ; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
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121
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256 define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
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120
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257 bb0:
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258 %tmp = icmp ne i32 %arg1, 0
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259 br i1 %tmp, label %bb2, label %bb3
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260
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261 bb2:
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262 store volatile i32 17, i32 addrspace(1)* undef
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263 br label %bb4
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264
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265 bb3:
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266 ; 32 byte asm
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267 call void asm sideeffect
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268 "v_nop_e64
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269 v_nop_e64
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270 v_nop_e64
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271 v_nop_e64", ""() #0
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272 br label %bb4
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273
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274 bb4:
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275 store volatile i32 63, i32 addrspace(1)* %arg
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276 ret void
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277 }
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278
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279 ; GCN-LABEL: {{^}}uniform_unconditional_min_long_backward_branch:
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134
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280 ; GCN-NEXT: ; %bb.0: ; %entry
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120
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281
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282 ; GCN-NEXT: [[LOOP:BB[0-9]_[0-9]+]]: ; %loop
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283 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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284 ; GCN-NEXT: ;;#ASMSTART
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285 ; GCN-NEXT: v_nop_e64
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286 ; GCN-NEXT: v_nop_e64
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287 ; GCN-NEXT: v_nop_e64
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288 ; GCN-NEXT: v_nop_e64
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289 ; GCN-NEXT: ;;#ASMEND
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290
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291 ; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
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292 ; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1
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147
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293
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294 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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295 ; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONGBB]]+4)-[[LOOP]]
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296 ; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0{{$}}
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297 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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120
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298 ; GCN-NEXT .Lfunc_end{{[0-9]+}}:
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121
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299 define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
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120
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300 entry:
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301 br label %loop
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302
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303 loop:
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304 ; 32 byte asm
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305 call void asm sideeffect
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306 "v_nop_e64
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307 v_nop_e64
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308 v_nop_e64
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309 v_nop_e64", ""() #0
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310 br label %loop
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311 }
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312
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313 ; Expansion of branch from %bb1 to %bb3 introduces need to expand
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314 ; branch from %bb0 to %bb2
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315
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316 ; GCN-LABEL: {{^}}expand_requires_expand:
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134
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317 ; GCN-NEXT: ; %bb.0: ; %bb0
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120
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318 ; GCN: s_load_dword
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319 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 0{{$}}
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320 ; GCN-NEXT: s_cbranch_scc0 [[BB1:BB[0-9]+_[0-9]+]]
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321
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322 ; GCN-NEXT: [[LONGBB0:BB[0-9]+_[0-9]+]]: ; %bb0
|
|
147
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323
|
|
|
324 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
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|
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325 ; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB0]]+4)
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|
326 ; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], 0{{$}}
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|
|
327 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}}
|
|
120
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328
|
|
|
329 ; GCN-NEXT: [[BB1]]: ; %bb1
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330 ; GCN-NEXT: s_load_dword
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331 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
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332 ; GCN-NEXT: s_cmp_eq_u32 s{{[0-9]+}}, 3{{$}}
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333 ; GCN-NEXT: s_cbranch_scc0 [[BB2:BB[0-9]_[0-9]+]]
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334
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335 ; GCN-NEXT: [[LONGBB1:BB[0-9]+_[0-9]+]]: ; %bb1
|
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147
|
336 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
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|
|
337 ; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB3:BB[0-9]+_[0-9]+]]-([[LONGBB1]]+4)
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|
|
338 ; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}}
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|
|
339 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
|
|
120
|
340
|
|
|
341 ; GCN-NEXT: [[BB2]]: ; %bb2
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|
|
342 ; GCN-NEXT: ;;#ASMSTART
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|
|
343 ; GCN-NEXT: v_nop_e64
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344 ; GCN-NEXT: v_nop_e64
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|
|
345 ; GCN-NEXT: v_nop_e64
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|
|
346 ; GCN-NEXT: v_nop_e64
|
|
|
347 ; GCN-NEXT: ;;#ASMEND
|
|
|
348
|
|
|
349 ; GCN-NEXT: [[BB3]]: ; %bb3
|
|
121
|
350 ; GCN-NEXT: ;;#ASMSTART
|
|
|
351 ; GCN-NEXT: v_nop_e64
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|
|
352 ; GCN-NEXT: ;;#ASMEND
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|
|
353 ; GCN-NEXT: ;;#ASMSTART
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|
|
354 ; GCN-NEXT: v_nop_e64
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|
|
355 ; GCN-NEXT: ;;#ASMEND
|
|
120
|
356 ; GCN-NEXT: s_endpgm
|
|
121
|
357 define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
|
|
120
|
358 bb0:
|
|
|
359 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
360 %cmp0 = icmp slt i32 %cond0, 0
|
|
|
361 br i1 %cmp0, label %bb2, label %bb1
|
|
|
362
|
|
|
363 bb1:
|
|
134
|
364 %val = load volatile i32, i32 addrspace(4)* undef
|
|
120
|
365 %cmp1 = icmp eq i32 %val, 3
|
|
|
366 br i1 %cmp1, label %bb3, label %bb2
|
|
|
367
|
|
|
368 bb2:
|
|
|
369 call void asm sideeffect
|
|
|
370 "v_nop_e64
|
|
|
371 v_nop_e64
|
|
|
372 v_nop_e64
|
|
|
373 v_nop_e64", ""() #0
|
|
|
374 br label %bb3
|
|
|
375
|
|
|
376 bb3:
|
|
121
|
377 ; These NOPs prevent tail-duplication-based outlining
|
|
|
378 ; from firing, which defeats the need to expand the branches and this test.
|
|
|
379 call void asm sideeffect
|
|
|
380 "v_nop_e64", ""() #0
|
|
|
381 call void asm sideeffect
|
|
|
382 "v_nop_e64", ""() #0
|
|
120
|
383 ret void
|
|
|
384 }
|
|
|
385
|
|
|
386 ; Requires expanding of required skip branch.
|
|
|
387
|
|
|
388 ; GCN-LABEL: {{^}}uniform_inside_divergent:
|
|
|
389 ; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
|
|
|
390 ; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
|
|
391 ; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9]+_[0-9]+]]
|
|
|
392 ; GCN-NEXT: s_cbranch_execnz [[IF:BB[0-9]+_[0-9]+]]
|
|
|
393
|
|
|
394 ; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %entry
|
|
147
|
395 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
|
|
|
396 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB]]+4)
|
|
|
397 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0{{$}}
|
|
|
398 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
|
|
120
|
399
|
|
|
400 ; GCN-NEXT: [[IF]]: ; %if
|
|
|
401 ; GCN: buffer_store_dword
|
|
|
402 ; GCN: s_cmp_lg_u32
|
|
|
403 ; GCN: s_cbranch_scc1 [[ENDIF]]
|
|
|
404
|
|
134
|
405 ; GCN-NEXT: ; %bb.2: ; %if_uniform
|
|
120
|
406 ; GCN: buffer_store_dword
|
|
|
407
|
|
|
408 ; GCN-NEXT: [[ENDIF]]: ; %endif
|
|
|
409 ; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]
|
|
121
|
410 ; GCN-NEXT: s_sleep 5
|
|
120
|
411 ; GCN-NEXT: s_endpgm
|
|
121
|
412 define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) #0 {
|
|
120
|
413 entry:
|
|
|
414 %tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
415 %d_cmp = icmp ult i32 %tid, 16
|
|
|
416 br i1 %d_cmp, label %if, label %endif
|
|
|
417
|
|
|
418 if:
|
|
|
419 store i32 0, i32 addrspace(1)* %out
|
|
|
420 %u_cmp = icmp eq i32 %cond, 0
|
|
|
421 br i1 %u_cmp, label %if_uniform, label %endif
|
|
|
422
|
|
|
423 if_uniform:
|
|
|
424 store i32 1, i32 addrspace(1)* %out
|
|
|
425 br label %endif
|
|
|
426
|
|
|
427 endif:
|
|
121
|
428 ; layout can remove the split branch if it can copy the return block.
|
|
|
429 ; This call makes the return block long enough that it doesn't get copied.
|
|
|
430 call void @llvm.amdgcn.s.sleep(i32 5);
|
|
120
|
431 ret void
|
|
|
432 }
|
|
|
433
|
|
|
434 ; si_mask_branch
|
|
|
435
|
|
|
436 ; GCN-LABEL: {{^}}analyze_mask_branch:
|
|
147
|
437 ; GCN: v_cmp_nlt_f32_e32 vcc
|
|
|
438 ; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
|
|
439 ; GCN-NEXT: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]]
|
|
|
440 ; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]
|
|
|
441
|
|
|
442 ; GCN: [[FLOW]]: ; %Flow
|
|
|
443 ; GCN-NEXT: s_or_saveexec_b64 [[TEMP_MASK1:s\[[0-9]+:[0-9]+\]]], [[MASK]]
|
|
|
444 ; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]]
|
|
120
|
445 ; GCN-NEXT: ; mask branch [[RET:BB[0-9]+_[0-9]+]]
|
|
|
446
|
|
147
|
447 ; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop{{$}}
|
|
120
|
448 ; GCN: ;;#ASMSTART
|
|
|
449 ; GCN: v_nop_e64
|
|
|
450 ; GCN: v_nop_e64
|
|
|
451 ; GCN: v_nop_e64
|
|
|
452 ; GCN: v_nop_e64
|
|
|
453 ; GCN: v_nop_e64
|
|
|
454 ; GCN: v_nop_e64
|
|
|
455 ; GCN: ;;#ASMEND
|
|
147
|
456 ; GCN: s_cbranch_vccz [[RET]]
|
|
120
|
457
|
|
147
|
458 ; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
|
|
120
|
459 ; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
|
|
147
|
460 ; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
|
|
|
461 ; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONGBB]]+4)-[[LOOP_BODY]]
|
|
|
462 ; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0
|
|
|
463 ; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
|
|
120
|
464
|
|
147
|
465 ; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
|
|
120
|
466 ; GCN-NEXT: s_endpgm
|
|
121
|
467 define amdgpu_kernel void @analyze_mask_branch() #0 {
|
|
120
|
468 entry:
|
|
|
469 %reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()
|
|
|
470 %cmp0 = fcmp ogt float %reg, 0.000000e+00
|
|
|
471 br i1 %cmp0, label %loop, label %ret
|
|
|
472
|
|
|
473 loop:
|
|
|
474 %phi = phi float [ 0.000000e+00, %loop_body ], [ 1.000000e+00, %entry ]
|
|
|
475 call void asm sideeffect
|
|
|
476 "v_nop_e64
|
|
|
477 v_nop_e64", ""() #0
|
|
|
478 %cmp1 = fcmp olt float %phi, 8.0
|
|
|
479 br i1 %cmp1, label %loop_body, label %ret
|
|
|
480
|
|
|
481 loop_body:
|
|
|
482 call void asm sideeffect
|
|
|
483 "v_nop_e64
|
|
|
484 v_nop_e64
|
|
|
485 v_nop_e64
|
|
|
486 v_nop_e64", ""() #0
|
|
|
487 br label %loop
|
|
|
488
|
|
|
489 ret:
|
|
|
490 store volatile i32 7, i32 addrspace(1)* undef
|
|
|
491 ret void
|
|
|
492 }
|
|
|
493
|
|
|
494 ; GCN-LABEL: {{^}}long_branch_hang:
|
|
|
495 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
|
|
147
|
496 ; GCN: s_cbranch_scc1 {{BB[0-9]+_[0-9]+}}
|
|
121
|
497 ; GCN-NEXT: s_branch [[LONG_BR_0:BB[0-9]+_[0-9]+]]
|
|
|
498 ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
|
|
120
|
499
|
|
147
|
500 ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-(
|
|
|
501 ; GCN-NEXT: s_addc_u32
|
|
|
502 ; GCN-NEXT: s_setpc_b64
|
|
120
|
503
|
|
121
|
504 ; GCN-NEXT: [[LONG_BR_0]]:
|
|
120
|
505 ; GCN-DAG: v_cmp_lt_i32
|
|
|
506 ; GCN-DAG: v_cmp_gt_i32
|
|
|
507 ; GCN: s_cbranch_vccnz
|
|
|
508
|
|
|
509 ; GCN: s_setpc_b64
|
|
|
510 ; GCN: s_setpc_b64
|
|
|
511
|
|
|
512 ; GCN: [[LONG_BR_DEST0]]
|
|
134
|
513 ; GCN: s_cbranch_vccz
|
|
120
|
514 ; GCN: s_setpc_b64
|
|
|
515
|
|
|
516 ; GCN: s_endpgm
|
|
|
517 define amdgpu_kernel void @long_branch_hang(i32 addrspace(1)* nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 {
|
|
|
518 bb:
|
|
|
519 %tmp = icmp slt i32 %arg2, 9
|
|
|
520 %tmp6 = icmp eq i32 %arg1, 0
|
|
|
521 %tmp7 = icmp sgt i32 %arg4, 0
|
|
|
522 %tmp8 = icmp sgt i32 %arg4, 5
|
|
|
523 br i1 %tmp8, label %bb9, label %bb13
|
|
|
524
|
|
|
525 bb9: ; preds = %bb
|
|
|
526 %tmp10 = and i1 %tmp7, %tmp
|
|
|
527 %tmp11 = icmp slt i32 %arg3, %arg4
|
|
|
528 %tmp12 = or i1 %tmp11, %tmp7
|
|
|
529 br i1 %tmp12, label %bb19, label %bb14
|
|
|
530
|
|
|
531 bb13: ; preds = %bb
|
|
134
|
532 call void asm sideeffect
|
|
|
533 "v_nop_e64
|
|
|
534 v_nop_e64
|
|
|
535 v_nop_e64
|
|
|
536 v_nop_e64", ""() #0
|
|
120
|
537 br i1 %tmp6, label %bb19, label %bb14
|
|
|
538
|
|
|
539 bb14: ; preds = %bb13, %bb9
|
|
|
540 %tmp15 = icmp slt i32 %arg3, %arg4
|
|
|
541 %tmp16 = or i1 %tmp15, %tmp
|
|
|
542 %tmp17 = and i1 %tmp6, %tmp16
|
|
|
543 %tmp18 = zext i1 %tmp17 to i32
|
|
|
544 br label %bb19
|
|
|
545
|
|
|
546 bb19: ; preds = %bb14, %bb13, %bb9
|
|
|
547 %tmp20 = phi i32 [ undef, %bb9 ], [ undef, %bb13 ], [ %tmp18, %bb14 ]
|
|
|
548 %tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %arg5
|
|
|
549 store i32 %tmp20, i32 addrspace(1)* %tmp21, align 4
|
|
|
550 ret void
|
|
|
551 }
|
|
|
552
|
|
|
553 attributes #0 = { nounwind }
|
|
|
554 attributes #1 = { nounwind readnone }
|
