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annotate lib/Target/R600/AMDGPUInstrInfo.h @ 52:c22698ecb2a9

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modified CreateIdentifierInfo and create new function which was named 'CreateUniqueIdentifierInfo'.
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Wed, 15 Jan 2014 21:01:33 +0900
parents e4204d083e25
children 54457678186b
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1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 /// \file
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11 /// \brief Contains the definition of a TargetInstrInfo class that is common
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12 /// to all AMD GPUs.
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13 //
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14 //===----------------------------------------------------------------------===//
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15
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16 #ifndef AMDGPUINSTRUCTIONINFO_H
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17 #define AMDGPUINSTRUCTIONINFO_H
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18
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19 #include "AMDGPUInstrInfo.h"
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20 #include "AMDGPURegisterInfo.h"
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21 #include "llvm/Target/TargetInstrInfo.h"
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22 #include <map>
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23
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24 #define GET_INSTRINFO_HEADER
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25 #define GET_INSTRINFO_ENUM
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26 #define GET_INSTRINFO_OPERAND_ENUM
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27 #include "AMDGPUGenInstrInfo.inc"
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28
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29 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
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30 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
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31 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
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32 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
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33
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34 namespace llvm {
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35
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36 class AMDGPUTargetMachine;
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37 class MachineFunction;
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38 class MachineInstr;
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39 class MachineInstrBuilder;
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40
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41 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
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42 private:
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43 const AMDGPURegisterInfo RI;
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44 bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
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45 MachineBasicBlock &MBB) const;
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46 virtual void anchor();
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47 protected:
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48 TargetMachine &TM;
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49 public:
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50 explicit AMDGPUInstrInfo(TargetMachine &tm);
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51
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52 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
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53
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54 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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55 unsigned &DstReg, unsigned &SubIdx) const;
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56
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57 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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58 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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59 int &FrameIndex) const;
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60 bool hasLoadFromStackSlot(const MachineInstr *MI,
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61 const MachineMemOperand *&MMO,
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62 int &FrameIndex) const;
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63 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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64 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
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65 int &FrameIndex) const;
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66 bool hasStoreFromStackSlot(const MachineInstr *MI,
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67 const MachineMemOperand *&MMO,
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68 int &FrameIndex) const;
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69
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70 MachineInstr *
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71 convertToThreeAddress(MachineFunction::iterator &MFI,
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72 MachineBasicBlock::iterator &MBBI,
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73 LiveVariables *LV) const;
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74
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75
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76 virtual void copyPhysReg(MachineBasicBlock &MBB,
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77 MachineBasicBlock::iterator MI, DebugLoc DL,
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78 unsigned DestReg, unsigned SrcReg,
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79 bool KillSrc) const = 0;
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80
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81 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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82
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83 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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84 MachineBasicBlock::iterator MI,
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85 unsigned SrcReg, bool isKill, int FrameIndex,
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86 const TargetRegisterClass *RC,
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87 const TargetRegisterInfo *TRI) const;
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88 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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89 MachineBasicBlock::iterator MI,
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90 unsigned DestReg, int FrameIndex,
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91 const TargetRegisterClass *RC,
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92 const TargetRegisterInfo *TRI) const;
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93
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94 protected:
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95 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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96 MachineInstr *MI,
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97 const SmallVectorImpl<unsigned> &Ops,
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98 int FrameIndex) const;
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99 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
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100 MachineInstr *MI,
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101 const SmallVectorImpl<unsigned> &Ops,
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102 MachineInstr *LoadMI) const;
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103 /// \returns the smallest register index that will be accessed by an indirect
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104 /// read or write or -1 if indirect addressing is not used by this program.
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105 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
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106
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107 /// \returns the largest register index that will be accessed by an indirect
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108 /// read or write or -1 if indirect addressing is not used by this program.
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109 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
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110
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111 public:
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112 bool canFoldMemoryOperand(const MachineInstr *MI,
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113 const SmallVectorImpl<unsigned> &Ops) const;
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114 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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115 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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116 SmallVectorImpl<MachineInstr *> &NewMIs) const;
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117 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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118 SmallVectorImpl<SDNode *> &NewNodes) const;
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119 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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120 bool UnfoldLoad, bool UnfoldStore,
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121 unsigned *LoadRegIndex = 0) const;
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122 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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123 int64_t Offset1, int64_t Offset2,
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124 unsigned NumLoads) const;
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125
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126 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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127 void insertNoop(MachineBasicBlock &MBB,
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128 MachineBasicBlock::iterator MI) const;
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129 bool isPredicated(const MachineInstr *MI) const;
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130 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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131 const SmallVectorImpl<MachineOperand> &Pred2) const;
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132 bool DefinesPredicate(MachineInstr *MI,
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133 std::vector<MachineOperand> &Pred) const;
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134 bool isPredicable(MachineInstr *MI) const;
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135 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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136
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137 // Helper functions that check the opcode for status information
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138 bool isLoadInst(llvm::MachineInstr *MI) const;
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139 bool isExtLoadInst(llvm::MachineInstr *MI) const;
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140 bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
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141 bool isSExtLoadInst(llvm::MachineInstr *MI) const;
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142 bool isZExtLoadInst(llvm::MachineInstr *MI) const;
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143 bool isAExtLoadInst(llvm::MachineInstr *MI) const;
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144 bool isStoreInst(llvm::MachineInstr *MI) const;
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145 bool isTruncStoreInst(llvm::MachineInstr *MI) const;
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146 bool isRegisterStore(const MachineInstr &MI) const;
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147 bool isRegisterLoad(const MachineInstr &MI) const;
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148
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149 //===---------------------------------------------------------------------===//
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150 // Pure virtual funtions to be implemented by sub-classes.
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151 //===---------------------------------------------------------------------===//
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152
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153 virtual unsigned getIEQOpcode() const = 0;
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154 virtual bool isMov(unsigned opcode) const = 0;
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155
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156 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and
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157 /// \p Channel
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158 ///
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159 /// We model indirect addressing using a virtual address space that can be
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160 /// accesed with loads and stores. The "Indirect Address" is the memory
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161 /// address in this virtual address space that maps to the given \p RegIndex
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162 /// and \p Channel.
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163 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
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164 unsigned Channel) const = 0;
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165
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166 /// \returns The register class to be used for loading and storing values
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167 /// from an "Indirect Address" .
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168 virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
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169
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170 /// \brief Build instruction(s) for an indirect register write.
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171 ///
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172 /// \returns The instruction that performs the indirect register write
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173 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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174 MachineBasicBlock::iterator I,
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175 unsigned ValueReg, unsigned Address,
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176 unsigned OffsetReg) const = 0;
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177
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178 /// \brief Build instruction(s) for an indirect register read.
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179 ///
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180 /// \returns The instruction that performs the indirect register read
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181 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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182 MachineBasicBlock::iterator I,
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183 unsigned ValueReg, unsigned Address,
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184 unsigned OffsetReg) const = 0;
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185
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186
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187 /// \brief Convert the AMDIL MachineInstr to a supported ISA
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188 /// MachineInstr
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189 virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
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190 DebugLoc DL) const;
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191
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192 /// \brief Build a MOV instruction.
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193 virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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194 MachineBasicBlock::iterator I,
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195 unsigned DstReg, unsigned SrcReg) const = 0;
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196
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197 /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
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198 /// equivalent opcode that writes \p Channels Channels.
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199 int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
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200
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201 };
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202
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203 namespace AMDGPU {
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204 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
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205 } // End namespace AMDGPU
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206
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207 } // End llvm namespace
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208
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209 #define AMDGPU_FLAG_REGISTER_LOAD (UINT64_C(1) << 63)
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210 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
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211
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212 #endif // AMDGPUINSTRINFO_H