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1 //===- RISCV.cpp ----------------------------------------------------------===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8
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9 #include "InputFiles.h"
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10 #include "Symbols.h"
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11 #include "SyntheticSections.h"
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12 #include "Target.h"
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13
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14 using namespace llvm;
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15 using namespace llvm::object;
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16 using namespace llvm::support::endian;
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17 using namespace llvm::ELF;
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173
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18 using namespace lld;
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19 using namespace lld::elf;
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150
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20
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21 namespace {
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22
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23 class RISCV final : public TargetInfo {
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24 public:
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25 RISCV();
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26 uint32_t calcEFlags() const override;
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27 void writeGotHeader(uint8_t *buf) const override;
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28 void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
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29 void writePltHeader(uint8_t *buf) const override;
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30 void writePlt(uint8_t *buf, const Symbol &sym,
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31 uint64_t pltEntryAddr) const override;
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32 RelType getDynRel(RelType type) const override;
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33 RelExpr getRelExpr(RelType type, const Symbol &s,
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34 const uint8_t *loc) const override;
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35 void relocate(uint8_t *loc, const Relocation &rel,
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36 uint64_t val) const override;
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37 };
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38
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39 } // end anonymous namespace
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40
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41 const uint64_t dtpOffset = 0x800;
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42
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43 enum Op {
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44 ADDI = 0x13,
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45 AUIPC = 0x17,
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46 JALR = 0x67,
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47 LD = 0x3003,
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48 LW = 0x2003,
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49 SRLI = 0x5013,
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50 SUB = 0x40000033,
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51 };
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52
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53 enum Reg {
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54 X_RA = 1,
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55 X_T0 = 5,
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56 X_T1 = 6,
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57 X_T2 = 7,
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58 X_T3 = 28,
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59 };
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60
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61 static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
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62 static uint32_t lo12(uint32_t val) { return val & 4095; }
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63
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64 static uint32_t itype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t imm) {
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65 return op | (rd << 7) | (rs1 << 15) | (imm << 20);
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66 }
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67 static uint32_t rtype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t rs2) {
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68 return op | (rd << 7) | (rs1 << 15) | (rs2 << 20);
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69 }
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70 static uint32_t utype(uint32_t op, uint32_t rd, uint32_t imm) {
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71 return op | (rd << 7) | (imm << 12);
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72 }
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73
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74 RISCV::RISCV() {
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75 copyRel = R_RISCV_COPY;
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76 noneRel = R_RISCV_NONE;
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77 pltRel = R_RISCV_JUMP_SLOT;
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78 relativeRel = R_RISCV_RELATIVE;
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79 iRelativeRel = R_RISCV_IRELATIVE;
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80 if (config->is64) {
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81 symbolicRel = R_RISCV_64;
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82 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64;
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83 tlsOffsetRel = R_RISCV_TLS_DTPREL64;
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84 tlsGotRel = R_RISCV_TLS_TPREL64;
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85 } else {
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86 symbolicRel = R_RISCV_32;
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87 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD32;
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88 tlsOffsetRel = R_RISCV_TLS_DTPREL32;
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89 tlsGotRel = R_RISCV_TLS_TPREL32;
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90 }
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91 gotRel = symbolicRel;
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92
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93 // .got[0] = _DYNAMIC
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94 gotBaseSymInGotPlt = false;
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95 gotHeaderEntriesNum = 1;
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96
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97 // .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
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98 gotPltHeaderEntriesNum = 2;
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99
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100 pltHeaderSize = 32;
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101 pltEntrySize = 16;
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102 ipltEntrySize = 16;
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103 }
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104
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105 static uint32_t getEFlags(InputFile *f) {
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106 if (config->is64)
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107 return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader()->e_flags;
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108 return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader()->e_flags;
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109 }
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110
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111 uint32_t RISCV::calcEFlags() const {
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112 // If there are only binary input files (from -b binary), use a
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113 // value of 0 for the ELF header flags.
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114 if (objectFiles.empty())
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115 return 0;
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116
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117 uint32_t target = getEFlags(objectFiles.front());
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118
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119 for (InputFile *f : objectFiles) {
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120 uint32_t eflags = getEFlags(f);
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121 if (eflags & EF_RISCV_RVC)
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122 target |= EF_RISCV_RVC;
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123
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124 if ((eflags & EF_RISCV_FLOAT_ABI) != (target & EF_RISCV_FLOAT_ABI))
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125 error(toString(f) +
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126 ": cannot link object files with different floating-point ABI");
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127
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128 if ((eflags & EF_RISCV_RVE) != (target & EF_RISCV_RVE))
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129 error(toString(f) +
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130 ": cannot link object files with different EF_RISCV_RVE");
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131 }
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132
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133 return target;
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134 }
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135
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136 void RISCV::writeGotHeader(uint8_t *buf) const {
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137 if (config->is64)
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138 write64le(buf, mainPart->dynamic->getVA());
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139 else
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140 write32le(buf, mainPart->dynamic->getVA());
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141 }
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142
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143 void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
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144 if (config->is64)
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145 write64le(buf, in.plt->getVA());
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146 else
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147 write32le(buf, in.plt->getVA());
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148 }
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149
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150 void RISCV::writePltHeader(uint8_t *buf) const {
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151 // 1: auipc t2, %pcrel_hi(.got.plt)
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152 // sub t1, t1, t3
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153 // l[wd] t3, %pcrel_lo(1b)(t2); t3 = _dl_runtime_resolve
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154 // addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0]
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155 // addi t0, t2, %pcrel_lo(1b)
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156 // srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0]
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157 // l[wd] t0, Wordsize(t0); t0 = link_map
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158 // jr t3
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159 uint32_t offset = in.gotPlt->getVA() - in.plt->getVA();
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160 uint32_t load = config->is64 ? LD : LW;
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161 write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset)));
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162 write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3));
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163 write32le(buf + 8, itype(load, X_T3, X_T2, lo12(offset)));
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164 write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12));
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165 write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset)));
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166 write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2));
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167 write32le(buf + 24, itype(load, X_T0, X_T0, config->wordsize));
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168 write32le(buf + 28, itype(JALR, 0, X_T3, 0));
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169 }
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170
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171 void RISCV::writePlt(uint8_t *buf, const Symbol &sym,
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172 uint64_t pltEntryAddr) const {
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173 // 1: auipc t3, %pcrel_hi(f@.got.plt)
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174 // l[wd] t3, %pcrel_lo(1b)(t3)
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175 // jalr t1, t3
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176 // nop
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177 uint32_t offset = sym.getGotPltVA() - pltEntryAddr;
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178 write32le(buf + 0, utype(AUIPC, X_T3, hi20(offset)));
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179 write32le(buf + 4, itype(config->is64 ? LD : LW, X_T3, X_T3, lo12(offset)));
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180 write32le(buf + 8, itype(JALR, X_T1, X_T3, 0));
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181 write32le(buf + 12, itype(ADDI, 0, 0, 0));
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182 }
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183
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184 RelType RISCV::getDynRel(RelType type) const {
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185 return type == target->symbolicRel ? type
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186 : static_cast<RelType>(R_RISCV_NONE);
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187 }
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188
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189 RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
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190 const uint8_t *loc) const {
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191 switch (type) {
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192 case R_RISCV_NONE:
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193 return R_NONE;
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194 case R_RISCV_32:
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195 case R_RISCV_64:
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196 case R_RISCV_HI20:
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197 case R_RISCV_LO12_I:
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198 case R_RISCV_LO12_S:
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199 case R_RISCV_RVC_LUI:
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200 return R_ABS;
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201 case R_RISCV_ADD8:
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202 case R_RISCV_ADD16:
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203 case R_RISCV_ADD32:
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204 case R_RISCV_ADD64:
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205 case R_RISCV_SET6:
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206 case R_RISCV_SET8:
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207 case R_RISCV_SET16:
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208 case R_RISCV_SET32:
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209 case R_RISCV_SUB6:
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210 case R_RISCV_SUB8:
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211 case R_RISCV_SUB16:
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212 case R_RISCV_SUB32:
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213 case R_RISCV_SUB64:
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214 return R_RISCV_ADD;
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215 case R_RISCV_JAL:
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216 case R_RISCV_BRANCH:
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217 case R_RISCV_PCREL_HI20:
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218 case R_RISCV_RVC_BRANCH:
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219 case R_RISCV_RVC_JUMP:
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220 case R_RISCV_32_PCREL:
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221 return R_PC;
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222 case R_RISCV_CALL:
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223 case R_RISCV_CALL_PLT:
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224 return R_PLT_PC;
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225 case R_RISCV_GOT_HI20:
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226 return R_GOT_PC;
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227 case R_RISCV_PCREL_LO12_I:
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228 case R_RISCV_PCREL_LO12_S:
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229 return R_RISCV_PC_INDIRECT;
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230 case R_RISCV_TLS_GD_HI20:
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231 return R_TLSGD_PC;
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232 case R_RISCV_TLS_GOT_HI20:
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233 config->hasStaticTlsModel = true;
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234 return R_GOT_PC;
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235 case R_RISCV_TPREL_HI20:
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236 case R_RISCV_TPREL_LO12_I:
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237 case R_RISCV_TPREL_LO12_S:
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238 return R_TLS;
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239 case R_RISCV_RELAX:
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240 case R_RISCV_TPREL_ADD:
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241 return R_NONE;
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242 case R_RISCV_ALIGN:
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243 // Not just a hint; always padded to the worst-case number of NOPs, so may
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244 // not currently be aligned, and without linker relaxation support we can't
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245 // delete NOPs to realign.
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246 errorOrWarn(getErrorLocation(loc) + "relocation R_RISCV_ALIGN requires "
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247 "unimplemented linker relaxation; recompile with -mno-relax");
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248 return R_NONE;
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249 default:
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250 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
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251 ") against symbol " + toString(s));
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252 return R_NONE;
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253 }
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254 }
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255
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256 // Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63.
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257 static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) {
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258 return (v & ((1ULL << (begin + 1)) - 1)) >> end;
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259 }
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260
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261 void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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262 const unsigned bits = config->wordsize * 8;
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263
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264 switch (rel.type) {
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265 case R_RISCV_32:
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266 write32le(loc, val);
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267 return;
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268 case R_RISCV_64:
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269 write64le(loc, val);
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270 return;
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271
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272 case R_RISCV_RVC_BRANCH: {
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273 checkInt(loc, static_cast<int64_t>(val) >> 1, 8, rel);
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274 checkAlignment(loc, val, 2, rel);
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275 uint16_t insn = read16le(loc) & 0xE383;
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276 uint16_t imm8 = extractBits(val, 8, 8) << 12;
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277 uint16_t imm4_3 = extractBits(val, 4, 3) << 10;
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278 uint16_t imm7_6 = extractBits(val, 7, 6) << 5;
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279 uint16_t imm2_1 = extractBits(val, 2, 1) << 3;
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280 uint16_t imm5 = extractBits(val, 5, 5) << 2;
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281 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5;
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282
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283 write16le(loc, insn);
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284 return;
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285 }
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286
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287 case R_RISCV_RVC_JUMP: {
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288 checkInt(loc, static_cast<int64_t>(val) >> 1, 11, rel);
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289 checkAlignment(loc, val, 2, rel);
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290 uint16_t insn = read16le(loc) & 0xE003;
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291 uint16_t imm11 = extractBits(val, 11, 11) << 12;
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292 uint16_t imm4 = extractBits(val, 4, 4) << 11;
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293 uint16_t imm9_8 = extractBits(val, 9, 8) << 9;
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294 uint16_t imm10 = extractBits(val, 10, 10) << 8;
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295 uint16_t imm6 = extractBits(val, 6, 6) << 7;
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296 uint16_t imm7 = extractBits(val, 7, 7) << 6;
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297 uint16_t imm3_1 = extractBits(val, 3, 1) << 3;
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298 uint16_t imm5 = extractBits(val, 5, 5) << 2;
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299 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5;
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300
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301 write16le(loc, insn);
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302 return;
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303 }
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304
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305 case R_RISCV_RVC_LUI: {
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306 int64_t imm = SignExtend64(val + 0x800, bits) >> 12;
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307 checkInt(loc, imm, 6, rel);
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308 if (imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
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309 write16le(loc, (read16le(loc) & 0x0F83) | 0x4000);
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310 } else {
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311 uint16_t imm17 = extractBits(val + 0x800, 17, 17) << 12;
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312 uint16_t imm16_12 = extractBits(val + 0x800, 16, 12) << 2;
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313 write16le(loc, (read16le(loc) & 0xEF83) | imm17 | imm16_12);
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314 }
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315 return;
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316 }
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317
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318 case R_RISCV_JAL: {
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319 checkInt(loc, static_cast<int64_t>(val) >> 1, 20, rel);
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320 checkAlignment(loc, val, 2, rel);
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321
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322 uint32_t insn = read32le(loc) & 0xFFF;
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323 uint32_t imm20 = extractBits(val, 20, 20) << 31;
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324 uint32_t imm10_1 = extractBits(val, 10, 1) << 21;
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325 uint32_t imm11 = extractBits(val, 11, 11) << 20;
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326 uint32_t imm19_12 = extractBits(val, 19, 12) << 12;
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327 insn |= imm20 | imm10_1 | imm11 | imm19_12;
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328
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329 write32le(loc, insn);
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330 return;
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331 }
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332
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333 case R_RISCV_BRANCH: {
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334 checkInt(loc, static_cast<int64_t>(val) >> 1, 12, rel);
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335 checkAlignment(loc, val, 2, rel);
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336
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337 uint32_t insn = read32le(loc) & 0x1FFF07F;
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338 uint32_t imm12 = extractBits(val, 12, 12) << 31;
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339 uint32_t imm10_5 = extractBits(val, 10, 5) << 25;
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340 uint32_t imm4_1 = extractBits(val, 4, 1) << 8;
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341 uint32_t imm11 = extractBits(val, 11, 11) << 7;
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342 insn |= imm12 | imm10_5 | imm4_1 | imm11;
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343
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344 write32le(loc, insn);
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345 return;
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346 }
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347
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348 // auipc + jalr pair
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349 case R_RISCV_CALL:
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350 case R_RISCV_CALL_PLT: {
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351 int64_t hi = SignExtend64(val + 0x800, bits) >> 12;
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352 checkInt(loc, hi, 20, rel);
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353 if (isInt<20>(hi)) {
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354 relocateNoSym(loc, R_RISCV_PCREL_HI20, val);
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355 relocateNoSym(loc + 4, R_RISCV_PCREL_LO12_I, val);
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356 }
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357 return;
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358 }
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359
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360 case R_RISCV_GOT_HI20:
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361 case R_RISCV_PCREL_HI20:
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362 case R_RISCV_TLS_GD_HI20:
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363 case R_RISCV_TLS_GOT_HI20:
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364 case R_RISCV_TPREL_HI20:
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365 case R_RISCV_HI20: {
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366 uint64_t hi = val + 0x800;
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367 checkInt(loc, SignExtend64(hi, bits) >> 12, 20, rel);
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368 write32le(loc, (read32le(loc) & 0xFFF) | (hi & 0xFFFFF000));
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369 return;
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370 }
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371
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372 case R_RISCV_PCREL_LO12_I:
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373 case R_RISCV_TPREL_LO12_I:
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374 case R_RISCV_LO12_I: {
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375 uint64_t hi = (val + 0x800) >> 12;
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376 uint64_t lo = val - (hi << 12);
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377 write32le(loc, (read32le(loc) & 0xFFFFF) | ((lo & 0xFFF) << 20));
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378 return;
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379 }
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380
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381 case R_RISCV_PCREL_LO12_S:
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382 case R_RISCV_TPREL_LO12_S:
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383 case R_RISCV_LO12_S: {
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384 uint64_t hi = (val + 0x800) >> 12;
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385 uint64_t lo = val - (hi << 12);
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386 uint32_t imm11_5 = extractBits(lo, 11, 5) << 25;
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387 uint32_t imm4_0 = extractBits(lo, 4, 0) << 7;
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388 write32le(loc, (read32le(loc) & 0x1FFF07F) | imm11_5 | imm4_0);
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389 return;
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390 }
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391
|
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392 case R_RISCV_ADD8:
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393 *loc += val;
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394 return;
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395 case R_RISCV_ADD16:
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396 write16le(loc, read16le(loc) + val);
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397 return;
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398 case R_RISCV_ADD32:
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399 write32le(loc, read32le(loc) + val);
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400 return;
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401 case R_RISCV_ADD64:
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402 write64le(loc, read64le(loc) + val);
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|
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403 return;
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404 case R_RISCV_SUB6:
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|
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405 *loc = (*loc & 0xc0) | (((*loc & 0x3f) - val) & 0x3f);
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|
|
406 return;
|
|
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407 case R_RISCV_SUB8:
|
|
|
408 *loc -= val;
|
|
|
409 return;
|
|
|
410 case R_RISCV_SUB16:
|
|
|
411 write16le(loc, read16le(loc) - val);
|
|
|
412 return;
|
|
|
413 case R_RISCV_SUB32:
|
|
|
414 write32le(loc, read32le(loc) - val);
|
|
|
415 return;
|
|
|
416 case R_RISCV_SUB64:
|
|
|
417 write64le(loc, read64le(loc) - val);
|
|
|
418 return;
|
|
|
419 case R_RISCV_SET6:
|
|
|
420 *loc = (*loc & 0xc0) | (val & 0x3f);
|
|
|
421 return;
|
|
|
422 case R_RISCV_SET8:
|
|
|
423 *loc = val;
|
|
|
424 return;
|
|
|
425 case R_RISCV_SET16:
|
|
|
426 write16le(loc, val);
|
|
|
427 return;
|
|
|
428 case R_RISCV_SET32:
|
|
|
429 case R_RISCV_32_PCREL:
|
|
|
430 write32le(loc, val);
|
|
|
431 return;
|
|
|
432
|
|
|
433 case R_RISCV_TLS_DTPREL32:
|
|
|
434 write32le(loc, val - dtpOffset);
|
|
|
435 break;
|
|
|
436 case R_RISCV_TLS_DTPREL64:
|
|
|
437 write64le(loc, val - dtpOffset);
|
|
|
438 break;
|
|
|
439
|
|
|
440 case R_RISCV_RELAX:
|
|
|
441 return; // Ignored (for now)
|
|
|
442
|
|
|
443 default:
|
|
|
444 llvm_unreachable("unknown relocation");
|
|
|
445 }
|
|
|
446 }
|
|
|
447
|
|
173
|
448 TargetInfo *elf::getRISCVTargetInfo() {
|
|
150
|
449 static RISCV target;
|
|
|
450 return ⌖
|
|
|
451 }
|
