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1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 // Primary reference:
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11 // A2 Processor User's Manual.
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12 // IBM (as updated in) 2010.
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13
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14 //===----------------------------------------------------------------------===//
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15 // Functional units on the PowerPC A2 chip sets
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16 //
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17 def A2_XU : FuncUnit; // A2_XU pipeline
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18 def A2_FU : FuncUnit; // FI pipeline
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19
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20 //
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21 // This file defines the itinerary class data for the PPC A2 processor.
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22 //
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23 //===----------------------------------------------------------------------===//
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24
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25
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26 def PPCA2Itineraries : ProcessorItineraries<
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27 [A2_XU, A2_FU], [], [
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28 InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
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29 [1, 0, 0]>,
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30 InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
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31 [2, 0, 0]>,
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32 InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>],
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33 [2, 0, 0, 0]>,
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33
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34 InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
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35 [2, 0, 0]>,
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36 InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
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37 [39, 0, 0]>,
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38 InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
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39 [71, 0, 0]>,
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40 InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
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41 [5, 0, 0]>,
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42 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
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43 [5, 0, 0]>,
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44 InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
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45 [6, 0, 0]>,
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46 InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
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47 [2, 0, 0]>,
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48 InstrItinData<IIC_IntRotateD, [InstrStage<1, [A2_XU]>],
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49 [2, 0, 0]>,
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50 InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>],
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51 [2, 0, 0]>,
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52 InstrItinData<IIC_IntShift, [InstrStage<1, [A2_XU]>],
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53 [2, 0, 0]>,
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54 InstrItinData<IIC_IntTrapW, [InstrStage<1, [A2_XU]>],
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55 [2, 0]>,
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56 InstrItinData<IIC_IntTrapD, [InstrStage<1, [A2_XU]>],
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57 [2, 0]>,
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58 InstrItinData<IIC_BrB, [InstrStage<1, [A2_XU]>],
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59 [6, 0, 0]>,
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60 InstrItinData<IIC_BrCR, [InstrStage<1, [A2_XU]>],
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61 [1, 0, 0]>,
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62 InstrItinData<IIC_BrMCR, [InstrStage<1, [A2_XU]>],
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63 [5, 0, 0]>,
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64 InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>],
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65 [1, 0, 0]>,
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66 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>],
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67 [1, 0, 0]>,
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68 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>],
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69 [1, 0, 0]>,
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70 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>],
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71 [1, 0, 0]>,
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72 InstrItinData<IIC_LdStLoad, [InstrStage<1, [A2_XU]>],
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73 [6, 0, 0]>,
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74 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
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75 [6, 8, 0, 0]>,
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76 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>],
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77 [6, 8, 0, 0]>,
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78 InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>],
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79 [6, 0, 0]>,
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80 InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>],
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81 [6, 0, 0]>,
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82 InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
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83 [0, 0, 0]>,
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84 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
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85 [2, 0, 0, 0]>,
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86 InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>],
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87 [16, 0, 0]>,
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88 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>],
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89 [0, 0, 0]>,
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90 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>],
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91 [2, 0, 0, 0]>,
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92 InstrItinData<IIC_LdStLFD, [InstrStage<1, [A2_XU]>],
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93 [7, 0, 0]>,
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94 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>],
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95 [7, 9, 0, 0]>,
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96 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [A2_XU]>],
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97 [7, 9, 0, 0]>,
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98 InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>],
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99 [6, 0, 0]>,
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100 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>],
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101 [6, 8, 0, 0]>,
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102 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [A2_XU]>],
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103 [6, 8, 0, 0]>,
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104 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
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105 [82, 0, 0]>, // L2 latency
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106 InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
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107 [0, 0, 0]>,
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108 InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>],
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109 [2, 0, 0, 0]>,
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110 InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [A2_XU]>],
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111 [2, 0, 0, 0]>,
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112 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
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113 [82, 0, 0]>, // L2 latency
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114 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
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115 [82, 0, 0]>, // L2 latency
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116 InstrItinData<IIC_LdStSync, [InstrStage<1, [A2_XU]>],
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117 [6]>,
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118 InstrItinData<IIC_SprISYNC, [InstrStage<1, [A2_XU]>],
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119 [16]>,
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120 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [A2_XU]>],
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121 [16, 0]>,
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122 InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>],
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123 [6, 0]>,
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124 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [A2_XU]>],
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125 [1, 0]>,
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126 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>],
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127 [4, 0]>,
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128 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>],
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129 [6, 0]>,
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130 InstrItinData<IIC_SprMFTB, [InstrStage<1, [A2_XU]>],
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131 [4, 0]>,
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132 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [A2_XU]>],
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133 [6, 0]>,
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134 InstrItinData<IIC_SprRFI, [InstrStage<1, [A2_XU]>],
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135 [16]>,
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136 InstrItinData<IIC_SprSC, [InstrStage<1, [A2_XU]>],
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137 [16]>,
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138 InstrItinData<IIC_FPGeneral, [InstrStage<1, [A2_FU]>],
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139 [6, 0, 0]>,
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140 InstrItinData<IIC_FPAddSub, [InstrStage<1, [A2_FU]>],
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141 [6, 0, 0]>,
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142 InstrItinData<IIC_FPCompare, [InstrStage<1, [A2_FU]>],
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143 [5, 0, 0]>,
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144 InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>],
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145 [72, 0, 0]>,
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146 InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>],
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147 [59, 0, 0]>,
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148 InstrItinData<IIC_FPSqrtD, [InstrStage<1, [A2_FU]>],
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149 [69, 0, 0]>,
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150 InstrItinData<IIC_FPSqrtS, [InstrStage<1, [A2_FU]>],
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151 [65, 0, 0]>,
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152 InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>],
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153 [6, 0, 0, 0]>,
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154 InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
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155 [6, 0]>
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156 ]>;
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157
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158 // ===---------------------------------------------------------------------===//
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159 // A2 machine model for scheduling and other instruction cost heuristics.
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160
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161 def PPCA2Model : SchedMachineModel {
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162 let IssueWidth = 1; // 1 instruction is dispatched per cycle.
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163 let LoadLatency = 6; // Optimistic load latency assuming bypass.
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164 // This is overriden by OperandCycles if the
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165 // Itineraries are queried instead.
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166 let MispredictPenalty = 13;
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167
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168 let CompleteModel = 0;
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169
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170 let Itineraries = PPCA2Itineraries;
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171 }
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172
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