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1 //===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file describes the RISC-V instructions from the standard 'A', Atomic
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11 // Instructions extension.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 //===----------------------------------------------------------------------===//
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16 // Instruction class templates
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17 //===----------------------------------------------------------------------===//
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18
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19 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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20 class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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21 : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
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22 (outs GPR:$rd), (ins GPR:$rs1),
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23 opcodestr, "$rd, (${rs1})"> {
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24 let rs2 = 0;
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25 }
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26
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27 multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
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28 def "" : LR_r<0, 0, funct3, opcodestr>;
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29 def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
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30 def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
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31 def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
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32 }
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33
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34 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
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35 class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
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36 : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
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37 (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
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38 opcodestr, "$rd, $rs2, (${rs1})">;
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39
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40 multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
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41 def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
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42 def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
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43 def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
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44 def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
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45 }
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46
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47 //===----------------------------------------------------------------------===//
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48 // Instructions
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49 //===----------------------------------------------------------------------===//
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50
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51 let Predicates = [HasStdExtA] in {
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52 defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
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53 defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
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54 defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
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55 defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
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56 defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
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57 defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
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58 defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
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59 defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
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60 defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
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61 defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
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62 defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
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63 } // Predicates = [HasStdExtA]
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64
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65 let Predicates = [HasStdExtA, IsRV64] in {
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66 defm LR_D : LR_r_aq_rl<0b011, "lr.d">;
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67 defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">;
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68 defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">;
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69 defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">;
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70 defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">;
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71 defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">;
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72 defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">;
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73 defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">;
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74 defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
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75 defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
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76 defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
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77 } // Predicates = [HasStedExtA, IsRV64]
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