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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // Implements the info about RISCV target spec.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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121
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14 #include "RISCV.h"
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15 #include "RISCVTargetMachine.h"
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16 #include "llvm/ADT/STLExtras.h"
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121
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17 #include "llvm/CodeGen/Passes.h"
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18 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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19 #include "llvm/CodeGen/TargetPassConfig.h"
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20 #include "llvm/IR/LegacyPassManager.h"
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21 #include "llvm/Support/FormattedStream.h"
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22 #include "llvm/Support/TargetRegistry.h"
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23 #include "llvm/Target/TargetOptions.h"
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24 using namespace llvm;
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25
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26 extern "C" void LLVMInitializeRISCVTarget() {
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27 RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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28 RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
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29 }
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30
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31 static std::string computeDataLayout(const Triple &TT) {
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32 if (TT.isArch64Bit()) {
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33 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
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34 } else {
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35 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
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36 return "e-m:e-p:32:32-i64:64-n32-S128";
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37 }
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38 }
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39
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40 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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41 Optional<Reloc::Model> RM) {
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42 if (!RM.hasValue())
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43 return Reloc::Static;
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44 return *RM;
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45 }
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46
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47 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
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48 if (CM)
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49 return *CM;
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50 return CodeModel::Small;
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51 }
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52
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53 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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54 StringRef CPU, StringRef FS,
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55 const TargetOptions &Options,
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56 Optional<Reloc::Model> RM,
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57 Optional<CodeModel::Model> CM,
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58 CodeGenOpt::Level OL, bool JIT)
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59 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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60 getEffectiveRelocModel(TT, RM),
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61 getEffectiveCodeModel(CM), OL),
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62 TLOF(make_unique<TargetLoweringObjectFileELF>()),
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63 Subtarget(TT, CPU, FS, *this) {
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64 initAsmInfo();
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65 }
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66
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67 namespace {
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68 class RISCVPassConfig : public TargetPassConfig {
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69 public:
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70 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
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71 : TargetPassConfig(TM, PM) {}
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72
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73 RISCVTargetMachine &getRISCVTargetMachine() const {
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74 return getTM<RISCVTargetMachine>();
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75 }
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76
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77 bool addInstSelector() override;
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78 void addPreEmitPass() override;
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79 };
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80 }
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81
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82 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
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83 return new RISCVPassConfig(*this, PM);
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84 }
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85
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86 bool RISCVPassConfig::addInstSelector() {
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87 addPass(createRISCVISelDag(getRISCVTargetMachine()));
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88
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89 return false;
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90 }
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91
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92 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
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