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annotate lib/Target/Mips/Mips16InstrInfo.h @ 33:e4204d083e25 LLVM3.5

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LLVM 3.5
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 14:32:10 +0900
parents 95c75e76d11b
children 54457678186b
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1 //===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef MIPS16INSTRUCTIONINFO_H
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15 #define MIPS16INSTRUCTIONINFO_H
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16
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17 #include "Mips16RegisterInfo.h"
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18 #include "MipsInstrInfo.h"
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19
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20 namespace llvm {
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21
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22 class Mips16InstrInfo : public MipsInstrInfo {
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23 const Mips16RegisterInfo RI;
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24
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25 public:
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26 explicit Mips16InstrInfo(MipsTargetMachine &TM);
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27
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28 virtual const MipsRegisterInfo &getRegisterInfo() const;
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29
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30 /// isLoadFromStackSlot - If the specified machine instruction is a direct
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31 /// load from a stack slot, return the virtual or physical register number of
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32 /// the destination along with the FrameIndex of the loaded stack slot. If
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33 /// not, return 0. This predicate must return 0 if the instruction has
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34 /// any side effects other than loading from the stack slot.
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35 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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36 int &FrameIndex) const;
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37
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38 /// isStoreToStackSlot - If the specified machine instruction is a direct
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39 /// store to a stack slot, return the virtual or physical register number of
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40 /// the source reg along with the FrameIndex of the loaded stack slot. If
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41 /// not, return 0. This predicate must return 0 if the instruction has
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42 /// any side effects other than storing to the stack slot.
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43 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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44 int &FrameIndex) const;
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45
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46 virtual void copyPhysReg(MachineBasicBlock &MBB,
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47 MachineBasicBlock::iterator MI, DebugLoc DL,
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48 unsigned DestReg, unsigned SrcReg,
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49 bool KillSrc) const;
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50
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51 virtual void storeRegToStack(MachineBasicBlock &MBB,
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52 MachineBasicBlock::iterator MBBI,
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53 unsigned SrcReg, bool isKill, int FrameIndex,
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54 const TargetRegisterClass *RC,
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55 const TargetRegisterInfo *TRI,
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56 int64_t Offset) const;
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57
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58 virtual void loadRegFromStack(MachineBasicBlock &MBB,
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59 MachineBasicBlock::iterator MBBI,
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60 unsigned DestReg, int FrameIndex,
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61 const TargetRegisterClass *RC,
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62 const TargetRegisterInfo *TRI,
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63 int64_t Offset) const;
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64
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65 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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66
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67 virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
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68
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69 // Adjust SP by FrameSize bytes. Save RA, S0, S1
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70 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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71 MachineBasicBlock::iterator I) const;
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72
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73 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
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74 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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75 MachineBasicBlock::iterator I) const;
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76
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77
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78 /// Adjust SP by Amount bytes.
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79 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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80 MachineBasicBlock::iterator I) const;
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81
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82 /// Emit a series of instructions to load an immediate.
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83 // This is to adjust some FrameReg. We return the new register to be used
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84 // in place of FrameReg and the adjusted immediate field (&NewImm)
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85 //
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86 unsigned loadImmediate(unsigned FrameReg,
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87 int64_t Imm, MachineBasicBlock &MBB,
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88 MachineBasicBlock::iterator II, DebugLoc DL,
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89 unsigned &NewImm) const;
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90
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91 static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
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92
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93 static bool validSpImm8(int offset) {
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94 return ((offset & 7) == 0) && isInt<11>(offset);
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95 }
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96
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97 //
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98 // build the proper one based on the Imm field
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99 //
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100
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101 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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102
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103 void BuildAddiuSpImm
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104 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
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105
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106 unsigned getInlineAsmLength(const char *Str,
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107 const MCAsmInfo &MAI) const;
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108 private:
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109 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
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110
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111 void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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112 unsigned Opc) const;
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113
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114 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
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115 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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116 MachineBasicBlock::iterator I,
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117 unsigned Reg1, unsigned Reg2) const;
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118
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119 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
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120 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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121 MachineBasicBlock &MBB,
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122 MachineBasicBlock::iterator I) const;
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123
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124 };
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125
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126 }
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127
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128 #endif