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1 //=- HexagonScheduleV67T.td - Hexagon V67 Tiny Core Scheduling Definitions --=//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8
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9 class HexagonV67TPseudoItin {
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10 list<InstrItinData> V67TPseudoItin_list = [
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11 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
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12 [Hex_FWD, Hex_FWD, Hex_FWD]>,
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13 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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14 InstrStage<1, [SLOT2, SLOT3]>],
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15 [2, 1, 1],
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16 [Hex_FWD, Hex_FWD, Hex_FWD]>,
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17 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>],
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18 [2, 1, 1]>,
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19 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
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20 ];
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21 }
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22
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23 // V67TItin_list and HVXItin contain some old itineraries
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24 // still used by a handful of instructions. Hopefully, we will be able to
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25 // get rid of them soon.
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26 def HexagonV67TItinList : DepScalarItinV67T,
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27 DepHVXItinV67, HVXItin, HexagonV67TPseudoItin {
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28 list<InstrItinData> V67TItin_list = [
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29 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>],
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30 [3, 1, 1],
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31 [Hex_FWD, Hex_FWD, Hex_FWD]>,
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32 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>],
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33 [1, 1, 3, 3],
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34 [Hex_FWD, Hex_FWD]>
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35 ];
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36
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37 list<InstrItinData> ItinList =
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38 !listconcat(DepScalarItinV67T_list,
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39 DepHVXItinV67_list, V67TItin_list,
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40 HVXItin_list, V67TPseudoItin_list);
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41 }
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42
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43 def HexagonItinerariesV67T :
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44 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
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45 CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
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46 CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
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47 CVI_ALL_NOMEM, CVI_ZW],
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48 [Hex_FWD, HVX_FWD],
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49 HexagonV67TItinList.ItinList>;
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50
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51
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52 def HexagonModelV67T : SchedMachineModel {
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53 let IssueWidth = 3;
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54 let Itineraries = HexagonItinerariesV67T;
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55 let LoadLatency = 1;
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56 let CompleteModel = 0;
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57 }
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58
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59 //===----------------------------------------------------------------------===//
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60 // Hexagon V67 Tiny Core Resource Definitions -
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61 //===----------------------------------------------------------------------===//
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