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annotate llvm/docs/AMDGPU/gfx10_addr_mimg.rst @ 235:edfff9242030 cbc-llvm13

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 21 Jul 2021 11:30:30 +0900
parents 2e18cbf3894f
children
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2 **************************************************
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3 * *
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4 * Automatically generated file, do not edit! *
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5 * *
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6 **************************************************
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8 .. _amdgpu_synid10_addr_mimg:
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10 vaddr
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11 ===========================
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13 Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
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15 This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
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17 *Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
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19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
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20 * If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
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23 *Operands:* :ref:`v<amdgpu_synid_v>`