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1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
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2 ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
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3
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4 ; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
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5 ; HSA: enable_sgpr_private_segment_buffer = 1
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6 ; HSA: enable_sgpr_dispatch_ptr = 0
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7 ; CI: enable_sgpr_queue_ptr = 1
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8 ; GFX9: enable_sgpr_queue_ptr = 0
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9
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10 ; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
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11 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
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12 ; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
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13 ; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1
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14 ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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15 ; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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16 ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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17
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18 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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19 ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
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20 ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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21 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
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22 ; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]]
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23
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24 ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base
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25 ; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1
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26 ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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27 ; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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28 ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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29
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30 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
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31
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32 ; At most 2 digits. Make sure src_shared_base is not counted as a high
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33 ; number SGPR.
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34
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35 ; CI: NumSgprs: {{[0-9][0-9]+}}
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36 ; GFX9: NumSgprs: {{[0-9]+}}
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37 define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 {
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38 %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
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39 store volatile i32 7, i32* %stof
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40 ret void
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41 }
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42
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173
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43 ; Test handling inside a non-kernel
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44 ; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast_func:
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45 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
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46 ; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
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47 ; CI-DAG: v_cmp_ne_u32_e32 vcc, -1, v0
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48 ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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49 ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0
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50
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51 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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52 ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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53 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
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54 ; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]]
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55
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56 ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base
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57 ; GFX9-DAG: v_cmp_ne_u32_e32 vcc, -1, v0
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58 ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0, vcc
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59 ; GFX9-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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60
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61 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
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62 define void @use_group_to_flat_addrspacecast_func(i32 addrspace(3)* %ptr) #0 {
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63 %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
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64 store volatile i32 7, i32* %stof
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65 ret void
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66 }
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67
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150
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68 ; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast:
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69 ; HSA: enable_sgpr_private_segment_buffer = 1
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70 ; HSA: enable_sgpr_dispatch_ptr = 0
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71 ; CI: enable_sgpr_queue_ptr = 1
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72 ; GFX9: enable_sgpr_queue_ptr = 0
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73
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74 ; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
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75 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}}
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76 ; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
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77
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78 ; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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79 ; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], 0
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80 ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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81 ; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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82 ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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83
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84 ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
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85 ; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
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86 ; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16
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87 ; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]]
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88
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89 ; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base
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90
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91 ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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92 ; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], 0
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93 ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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94 ; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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95 ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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96
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97 ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
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98
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99 ; CI: NumSgprs: {{[0-9][0-9]+}}
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100 ; GFX9: NumSgprs: {{[0-9]+}}
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101 define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 {
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102 %stof = addrspacecast i32 addrspace(5)* %ptr to i32*
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103 store volatile i32 7, i32* %stof
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104 ret void
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105 }
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106
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107 ; no-op
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108 ; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast:
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109 ; HSA: enable_sgpr_queue_ptr = 0
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110
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111 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
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112 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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113 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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114 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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115 ; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
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116 define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 {
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117 %stof = addrspacecast i32 addrspace(1)* %ptr to i32*
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118 store volatile i32 7, i32* %stof
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119 ret void
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120 }
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121
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122 ; no-op
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123 ; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
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124 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
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125 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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126 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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127 ; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
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128 define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 {
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129 %stof = addrspacecast i32 addrspace(4)* %ptr to i32*
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130 %ld = load volatile i32, i32* %stof
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131 ret void
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132 }
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133
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173
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134 ; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
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135 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
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136 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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137 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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138 ; HSA: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
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139 define amdgpu_kernel void @use_constant_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 {
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140 %stof = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)*
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141 %ld = load volatile i32, i32 addrspace(1)* %stof
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142 ret void
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143 }
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144
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150
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145 ; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast:
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146 ; HSA: enable_sgpr_private_segment_buffer = 1
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147 ; HSA: enable_sgpr_dispatch_ptr = 0
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148 ; HSA: enable_sgpr_queue_ptr = 0
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149
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150 ; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}
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151 ; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}}
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152 ; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
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153 ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
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154 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
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155 ; HSA: ds_write_b32 [[CASTPTR]], v[[K]]
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156 define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 {
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157 %ftos = addrspacecast i32* %ptr to i32 addrspace(3)*
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158 store volatile i32 0, i32 addrspace(3)* %ftos
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159 ret void
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160 }
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161
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162 ; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast:
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163 ; HSA: enable_sgpr_private_segment_buffer = 1
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164 ; HSA: enable_sgpr_dispatch_ptr = 0
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165 ; HSA: enable_sgpr_queue_ptr = 0
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166
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167 ; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}
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168 ; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}}
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169 ; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
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170 ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], 0, v[[VPTR_LO]]
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171 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
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173
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172 ; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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150
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173 define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 {
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174 %ftos = addrspacecast i32* %ptr to i32 addrspace(5)*
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175 store volatile i32 0, i32 addrspace(5)* %ftos
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176 ret void
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177 }
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178
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179 ; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast:
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180 ; HSA: enable_sgpr_queue_ptr = 0
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181
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182 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
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183 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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184 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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185 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0
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186 ; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
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187 define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 {
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188 %ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
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189 store volatile i32 0, i32 addrspace(1)* %ftos
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190 ret void
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191 }
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192
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193 ; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast:
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194 ; HSA: enable_sgpr_queue_ptr = 0
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195
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196 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
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197 ; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0
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198 define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 {
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199 %ftos = addrspacecast i32* %ptr to i32 addrspace(4)*
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200 load volatile i32, i32 addrspace(4)* %ftos
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201 ret void
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202 }
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203
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204 ; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast:
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205 ; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
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206 ; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
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207 ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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208 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
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209 ; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]]
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210
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211 ; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base
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212
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213 ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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214 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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215 ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
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216 define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 {
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217 %cast = addrspacecast i32 addrspace(3)* null to i32*
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218 store volatile i32 7, i32* %cast
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219 ret void
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220 }
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221
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222 ; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast:
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223 ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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224 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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225 ; HSA: ds_write_b32 [[PTR]], [[K]]
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226 define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 {
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227 %cast = addrspacecast i32* null to i32 addrspace(3)*
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228 store volatile i32 7, i32 addrspace(3)* %cast
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229 ret void
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230 }
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231
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232 ; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast:
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233 ; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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234 ; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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235 ; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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236 ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
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237 define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 {
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238 %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32*
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239 store volatile i32 7, i32* %cast
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240 ret void
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241 }
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242
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243 ; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast:
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244 ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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245 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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246 ; HSA: ds_write_b32 [[PTR]], [[K]]
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247 define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 {
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248 %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(3)*
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249 store volatile i32 7, i32 addrspace(3)* %cast
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250 ret void
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251 }
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252
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253 ; FIXME: Shouldn't need to enable queue ptr
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254 ; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast:
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255 ; CI: enable_sgpr_queue_ptr = 1
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256 ; GFX9: enable_sgpr_queue_ptr = 0
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257
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258 ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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259 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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260 ; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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261 ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
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262 define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
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263 %cast = addrspacecast i32 addrspace(5)* null to i32*
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264 store volatile i32 7, i32* %cast
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265 ret void
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266 }
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267
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268 ; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast:
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269 ; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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173
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270 ; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0
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150
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271 define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
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272 %cast = addrspacecast i32* null to i32 addrspace(5)*
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273 store volatile i32 7, i32 addrspace(5)* %cast
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274 ret void
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275 }
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276
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277 ; Disable optimizations in case there are optimizations added that
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278 ; specialize away generic pointer accesses.
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279
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280 ; HSA-LABEL: {{^}}branch_use_flat_i32:
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281 ; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}
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282 ; HSA: s_endpgm
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283 define amdgpu_kernel void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
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284 entry:
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285 %cmp = icmp ne i32 %c, 0
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286 br i1 %cmp, label %local, label %global
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287
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288 local:
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289 %flat_local = addrspacecast i32 addrspace(3)* %lptr to i32*
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290 br label %end
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291
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292 global:
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293 %flat_global = addrspacecast i32 addrspace(1)* %gptr to i32*
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294 br label %end
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295
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296 end:
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297 %fptr = phi i32* [ %flat_local, %local ], [ %flat_global, %global ]
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298 store volatile i32 %x, i32* %fptr, align 4
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299 ; %val = load i32, i32* %fptr, align 4
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300 ; store i32 %val, i32 addrspace(1)* %out, align 4
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301 ret void
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302 }
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303
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304 ; Check for prologue initializing special SGPRs pointing to scratch.
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305 ; HSA-LABEL: {{^}}store_flat_scratch:
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306 ; CI-DAG: s_mov_b32 flat_scratch_lo, s9
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307 ; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11
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308 ; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8
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309
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310 ; GFX9: s_add_u32 flat_scratch_lo, s6, s9
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311 ; GFX9: s_addc_u32 flat_scratch_hi, s7, 0
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312
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313 ; HSA: {{flat|global}}_store_dword
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314 ; HSA: s_barrier
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315 ; HSA: {{flat|global}}_load_dword
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316 define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
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317 %alloca = alloca i32, i32 9, align 4, addrspace(5)
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318 %x = call i32 @llvm.amdgcn.workitem.id.x() #2
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319 %pptr = getelementptr i32, i32 addrspace(5)* %alloca, i32 %x
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320 %fptr = addrspacecast i32 addrspace(5)* %pptr to i32*
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321 store volatile i32 %x, i32* %fptr
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322 ; Dummy call
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323 call void @llvm.amdgcn.s.barrier() #1
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324 %reload = load volatile i32, i32* %fptr, align 4
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325 store volatile i32 %reload, i32 addrspace(1)* %out, align 4
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326 ret void
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327 }
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328
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173
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329 ; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast
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330 ; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
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331 ; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
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332 ; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}}
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333 ; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
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334 ; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
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335 ; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}}
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336 define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(i8 addrspace(4)* addrspace(4)* %ptr.ptr, i32 %offset) #0 {
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337 %ptr = load volatile i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %ptr.ptr
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338 %addrspacecast = addrspacecast i8 addrspace(4)* %ptr to i8 addrspace(6)*
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339 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset
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340 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)*
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341 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4
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342 ret void
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343 }
|
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344
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345 ; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast
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346 ; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
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347 ; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
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348 ; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}}
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349 ; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
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350 ; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
|
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351 ; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}}
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352 define amdgpu_kernel void @use_global_to_constant32_addrspacecast(i8 addrspace(1)* addrspace(4)* %ptr.ptr, i32 %offset) #0 {
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353 %ptr = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* %ptr.ptr
|
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|
354 %addrspacecast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(6)*
|
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|
355 %gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset
|
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|
356 %ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)*
|
|
|
357 %load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4
|
|
|
358 ret void
|
|
|
359 }
|
|
|
360
|
|
150
|
361 declare void @llvm.amdgcn.s.barrier() #1
|
|
|
362 declare i32 @llvm.amdgcn.workitem.id.x() #2
|
|
|
363
|
|
|
364 attributes #0 = { nounwind }
|
|
|
365 attributes #1 = { nounwind convergent }
|
|
|
366 attributes #2 = { nounwind readnone }
|
