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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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3 ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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4 ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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5
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6 ; ===================================================================================
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7 ; V_AND_OR_B32
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8 ; ===================================================================================
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9
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10 define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
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11 ; VI-LABEL: and_or:
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12 ; VI: ; %bb.0:
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13 ; VI-NEXT: v_and_b32_e32 v0, v0, v1
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14 ; VI-NEXT: v_or_b32_e32 v0, v0, v2
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15 ; VI-NEXT: ; return to shader part epilog
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16 ;
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17 ; GFX9-LABEL: and_or:
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18 ; GFX9: ; %bb.0:
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19 ; GFX9-NEXT: v_and_or_b32 v0, v0, v1, v2
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20 ; GFX9-NEXT: ; return to shader part epilog
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21 ;
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22 ; GFX10-LABEL: and_or:
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23 ; GFX10: ; %bb.0:
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24 ; GFX10-NEXT: v_and_or_b32 v0, v0, v1, v2
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25 ; GFX10-NEXT: ; implicit-def: $vcc_hi
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26 ; GFX10-NEXT: ; return to shader part epilog
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27 %x = and i32 %a, %b
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28 %result = or i32 %x, %c
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29 %bc = bitcast i32 %result to float
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30 ret float %bc
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31 }
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32
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33 ; ThreeOp instruction variant not used due to Constant Bus Limitations
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34 define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
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35 ; VI-LABEL: and_or_vgpr_b:
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36 ; VI: ; %bb.0:
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37 ; VI-NEXT: v_and_b32_e32 v0, s2, v0
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38 ; VI-NEXT: v_or_b32_e32 v0, s3, v0
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39 ; VI-NEXT: ; return to shader part epilog
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40 ;
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41 ; GFX9-LABEL: and_or_vgpr_b:
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42 ; GFX9: ; %bb.0:
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43 ; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
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44 ; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
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45 ; GFX9-NEXT: ; return to shader part epilog
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46 ;
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47 ; GFX10-LABEL: and_or_vgpr_b:
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48 ; GFX10: ; %bb.0:
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49 ; GFX10-NEXT: v_and_or_b32 v0, s2, v0, s3
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50 ; GFX10-NEXT: ; implicit-def: $vcc_hi
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51 ; GFX10-NEXT: ; return to shader part epilog
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52 %x = and i32 %a, %b
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53 %result = or i32 %x, %c
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54 %bc = bitcast i32 %result to float
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55 ret float %bc
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56 }
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57
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58 define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
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59 ; VI-LABEL: and_or_vgpr_ab:
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60 ; VI: ; %bb.0:
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61 ; VI-NEXT: v_and_b32_e32 v0, v0, v1
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62 ; VI-NEXT: v_or_b32_e32 v0, s2, v0
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63 ; VI-NEXT: ; return to shader part epilog
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64 ;
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65 ; GFX9-LABEL: and_or_vgpr_ab:
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66 ; GFX9: ; %bb.0:
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67 ; GFX9-NEXT: v_and_or_b32 v0, v0, v1, s2
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68 ; GFX9-NEXT: ; return to shader part epilog
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69 ;
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70 ; GFX10-LABEL: and_or_vgpr_ab:
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71 ; GFX10: ; %bb.0:
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72 ; GFX10-NEXT: v_and_or_b32 v0, v0, v1, s2
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73 ; GFX10-NEXT: ; implicit-def: $vcc_hi
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74 ; GFX10-NEXT: ; return to shader part epilog
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75 %x = and i32 %a, %b
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76 %result = or i32 %x, %c
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77 %bc = bitcast i32 %result to float
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78 ret float %bc
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79 }
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80
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81 define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
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82 ; VI-LABEL: and_or_vgpr_const:
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83 ; VI: ; %bb.0:
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84 ; VI-NEXT: v_and_b32_e32 v0, 4, v0
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85 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
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86 ; VI-NEXT: ; return to shader part epilog
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87 ;
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88 ; GFX9-LABEL: and_or_vgpr_const:
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89 ; GFX9: ; %bb.0:
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90 ; GFX9-NEXT: v_and_or_b32 v0, v0, 4, v1
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91 ; GFX9-NEXT: ; return to shader part epilog
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92 ;
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93 ; GFX10-LABEL: and_or_vgpr_const:
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94 ; GFX10: ; %bb.0:
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95 ; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v1
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96 ; GFX10-NEXT: ; implicit-def: $vcc_hi
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97 ; GFX10-NEXT: ; return to shader part epilog
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98 %x = and i32 4, %a
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99 %result = or i32 %x, %b
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100 %bc = bitcast i32 %result to float
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101 ret float %bc
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102 }
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103
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104 define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
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105 ; VI-LABEL: and_or_vgpr_const_inline_const:
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106 ; VI: ; %bb.0:
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107 ; VI-NEXT: v_and_b32_e32 v0, 20, v0
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108 ; VI-NEXT: v_or_b32_e32 v0, 0x808, v0
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109 ; VI-NEXT: ; return to shader part epilog
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110 ;
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111 ; GFX9-LABEL: and_or_vgpr_const_inline_const:
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112 ; GFX9: ; %bb.0:
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113 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x808
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114 ; GFX9-NEXT: v_and_or_b32 v0, v0, 20, v1
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115 ; GFX9-NEXT: ; return to shader part epilog
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116 ;
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117 ; GFX10-LABEL: and_or_vgpr_const_inline_const:
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118 ; GFX10: ; %bb.0:
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119 ; GFX10-NEXT: v_and_or_b32 v0, v0, 20, 0x808
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120 ; GFX10-NEXT: ; implicit-def: $vcc_hi
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121 ; GFX10-NEXT: ; return to shader part epilog
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122 %x = and i32 20, %a
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123 %result = or i32 %x, 2056
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124 %bc = bitcast i32 %result to float
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125 ret float %bc
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126 }
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127
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128 define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
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129 ; VI-LABEL: and_or_vgpr_inline_const_x2:
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130 ; VI: ; %bb.0:
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131 ; VI-NEXT: v_and_b32_e32 v0, 4, v0
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132 ; VI-NEXT: v_or_b32_e32 v0, 1, v0
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133 ; VI-NEXT: ; return to shader part epilog
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134 ;
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135 ; GFX9-LABEL: and_or_vgpr_inline_const_x2:
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136 ; GFX9: ; %bb.0:
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137 ; GFX9-NEXT: v_and_or_b32 v0, v0, 4, 1
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138 ; GFX9-NEXT: ; return to shader part epilog
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139 ;
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140 ; GFX10-LABEL: and_or_vgpr_inline_const_x2:
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141 ; GFX10: ; %bb.0:
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142 ; GFX10-NEXT: v_and_or_b32 v0, v0, 4, 1
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143 ; GFX10-NEXT: ; implicit-def: $vcc_hi
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144 ; GFX10-NEXT: ; return to shader part epilog
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145 %x = and i32 4, %a
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146 %result = or i32 %x, 1
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147 %bc = bitcast i32 %result to float
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148 ret float %bc
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149 }
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