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annotate llvm/test/CodeGen/AMDGPU/bfe-patterns.ll @ 206:f17a3b42b08b

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Added tag before-12 for changeset b7591485f4cd
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 07 Jun 2021 21:25:57 +0900
parents 1d019706d866
children 2e18cbf3894f
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150
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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3
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4 ; GCN-LABEL: {{^}}v_ubfe_sub_i32:
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5 ; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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6 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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7 ; GCN: v_bfe_u32 v{{[0-9]+}}, [[SRC]], 0, [[WIDTH]]
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8 define amdgpu_kernel void @v_ubfe_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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9 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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10 %in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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11 %in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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12 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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13 %src = load volatile i32, i32 addrspace(1)* %in0.gep
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14 %width = load volatile i32, i32 addrspace(1)* %in0.gep
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15 %sub = sub i32 32, %width
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16 %shl = shl i32 %src, %sub
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17 %bfe = lshr i32 %shl, %sub
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18 store i32 %bfe, i32 addrspace(1)* %out.gep
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19 ret void
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20 }
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21
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22 ; GCN-LABEL: {{^}}v_ubfe_sub_multi_use_shl_i32:
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23 ; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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24 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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25 ; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
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26
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27 ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
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28 ; SI-NEXT: v_lshr_b32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
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29
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30 ; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
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31 ; VI-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
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32
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33 ; GCN: [[BFE]]
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34 ; GCN: [[SHL]]
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35 define amdgpu_kernel void @v_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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36 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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37 %in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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38 %in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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39 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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40 %src = load volatile i32, i32 addrspace(1)* %in0.gep
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41 %width = load volatile i32, i32 addrspace(1)* %in0.gep
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42 %sub = sub i32 32, %width
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43 %shl = shl i32 %src, %sub
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44 %bfe = lshr i32 %shl, %sub
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45 store i32 %bfe, i32 addrspace(1)* %out.gep
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46 store volatile i32 %shl, i32 addrspace(1)* undef
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47 ret void
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48 }
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49
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50 ; GCN-LABEL: {{^}}s_ubfe_sub_i32:
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51 ; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}}
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52 ; GCN: v_mov_b32_e32 [[VWIDTH:v[0-9]+]], s[[WIDTH]]
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53 ; GCN: v_bfe_u32 v{{[0-9]+}}, s[[SRC]], 0, [[VWIDTH]]
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54 define amdgpu_kernel void @s_ubfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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55 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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56 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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57 %sub = sub i32 32, %width
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58 %shl = shl i32 %src, %sub
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59 %bfe = lshr i32 %shl, %sub
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60 store i32 %bfe, i32 addrspace(1)* %out.gep
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61 ret void
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62 }
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63
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64 ; GCN-LABEL: {{^}}s_ubfe_sub_multi_use_shl_i32:
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65 ; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}}
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66 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
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67 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
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68 ; GCN: s_lshr_b32 s{{[0-9]+}}, [[SHL]], [[SUB]]
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69 define amdgpu_kernel void @s_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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70 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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71 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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72 %sub = sub i32 32, %width
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73 %shl = shl i32 %src, %sub
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74 %bfe = lshr i32 %shl, %sub
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75 store i32 %bfe, i32 addrspace(1)* %out.gep
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76 store volatile i32 %shl, i32 addrspace(1)* undef
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77 ret void
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78 }
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79
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80 ; GCN-LABEL: {{^}}v_sbfe_sub_i32:
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81 ; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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82 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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83 ; GCN: v_bfe_i32 v{{[0-9]+}}, [[SRC]], 0, [[WIDTH]]
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84 define amdgpu_kernel void @v_sbfe_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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85 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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86 %in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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87 %in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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88 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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89 %src = load volatile i32, i32 addrspace(1)* %in0.gep
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90 %width = load volatile i32, i32 addrspace(1)* %in0.gep
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91 %sub = sub i32 32, %width
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92 %shl = shl i32 %src, %sub
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93 %bfe = ashr i32 %shl, %sub
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94 store i32 %bfe, i32 addrspace(1)* %out.gep
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95 ret void
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96 }
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97
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98 ; GCN-LABEL: {{^}}v_sbfe_sub_multi_use_shl_i32:
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99 ; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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100 ; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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101 ; GCN: v_sub_{{[iu]}}32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
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102
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103 ; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
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104 ; SI-NEXT: v_ashr_i32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
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105
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106 ; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
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107 ; VI-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
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108
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109 ; GCN: [[BFE]]
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110 ; GCN: [[SHL]]
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111 define amdgpu_kernel void @v_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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112 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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113 %in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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114 %in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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115 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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116 %src = load volatile i32, i32 addrspace(1)* %in0.gep
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117 %width = load volatile i32, i32 addrspace(1)* %in0.gep
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118 %sub = sub i32 32, %width
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119 %shl = shl i32 %src, %sub
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120 %bfe = ashr i32 %shl, %sub
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121 store i32 %bfe, i32 addrspace(1)* %out.gep
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122 store volatile i32 %shl, i32 addrspace(1)* undef
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123 ret void
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124 }
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125
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126 ; GCN-LABEL: {{^}}s_sbfe_sub_i32:
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127 ; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}}
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128 ; GCN: v_mov_b32_e32 [[VWIDTH:v[0-9]+]], s[[WIDTH]]
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129 ; GCN: v_bfe_i32 v{{[0-9]+}}, s[[SRC]], 0, [[VWIDTH]]
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130 define amdgpu_kernel void @s_sbfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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131 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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132 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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133 %sub = sub i32 32, %width
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134 %shl = shl i32 %src, %sub
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135 %bfe = ashr i32 %shl, %sub
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136 store i32 %bfe, i32 addrspace(1)* %out.gep
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137 ret void
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138 }
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139
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140 ; GCN-LABEL: {{^}}s_sbfe_sub_multi_use_shl_i32:
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141 ; GCN: s_load_dwordx2 s{{\[}}[[SRC:[0-9]+]]:[[WIDTH:[0-9]+]]{{\]}}, s[0:1], {{0xb|0x2c}}
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142 ; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, s[[WIDTH]]
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143 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], s[[SRC]], [[SUB]]
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144 ; GCN: s_ashr_i32 s{{[0-9]+}}, [[SHL]], [[SUB]]
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145 define amdgpu_kernel void @s_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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146 %id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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147 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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148 %sub = sub i32 32, %width
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149 %shl = shl i32 %src, %sub
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150 %bfe = ashr i32 %shl, %sub
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151 store i32 %bfe, i32 addrspace(1)* %out.gep
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152 store volatile i32 %shl, i32 addrspace(1)* undef
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153 ret void
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154 }
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155
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156 declare i32 @llvm.amdgcn.workitem.id.x() #0
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157
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158 attributes #0 = { nounwind readnone }
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159 attributes #1 = { nounwind }