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1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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2 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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3
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4 ; GCN-LABEL: ds_read32_combine_stride_400:
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5 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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6 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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7
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8 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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9 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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10 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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11
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12 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]]
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13 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]]
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14 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]]
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15
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16 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
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17 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
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18 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
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19 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
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20 define amdgpu_kernel void @ds_read32_combine_stride_400(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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21 bb:
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22 %tmp = load float, float addrspace(3)* %arg, align 4
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23 %tmp2 = fadd float %tmp, 0.000000e+00
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24 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
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25 %tmp4 = load float, float addrspace(3)* %tmp3, align 4
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26 %tmp5 = fadd float %tmp2, %tmp4
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27 %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
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28 %tmp7 = load float, float addrspace(3)* %tmp6, align 4
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29 %tmp8 = fadd float %tmp5, %tmp7
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30 %tmp9 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
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31 %tmp10 = load float, float addrspace(3)* %tmp9, align 4
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32 %tmp11 = fadd float %tmp8, %tmp10
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33 %tmp12 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
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34 %tmp13 = load float, float addrspace(3)* %tmp12, align 4
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35 %tmp14 = fadd float %tmp11, %tmp13
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36 %tmp15 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
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37 %tmp16 = load float, float addrspace(3)* %tmp15, align 4
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38 %tmp17 = fadd float %tmp14, %tmp16
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39 %tmp18 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
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40 %tmp19 = load float, float addrspace(3)* %tmp18, align 4
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41 %tmp20 = fadd float %tmp17, %tmp19
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42 %tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
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43 %tmp22 = load float, float addrspace(3)* %tmp21, align 4
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44 %tmp23 = fadd float %tmp20, %tmp22
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45 store float %tmp23, float *%arg1, align 4
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46 ret void
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47 }
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48
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49 ; GCN-LABEL: ds_read32_combine_stride_400_back:
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50 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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51 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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52
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53 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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54 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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55 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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56
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57 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]]
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58 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]]
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59 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]]
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60
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61 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
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62 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100
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63 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100
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64 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:100
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65 define amdgpu_kernel void @ds_read32_combine_stride_400_back(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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66 bb:
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67 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
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68 %tmp2 = load float, float addrspace(3)* %tmp, align 4
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69 %tmp3 = fadd float %tmp2, 0.000000e+00
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70 %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
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71 %tmp5 = load float, float addrspace(3)* %tmp4, align 4
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72 %tmp6 = fadd float %tmp3, %tmp5
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73 %tmp7 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
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74 %tmp8 = load float, float addrspace(3)* %tmp7, align 4
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75 %tmp9 = fadd float %tmp6, %tmp8
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76 %tmp10 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
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77 %tmp11 = load float, float addrspace(3)* %tmp10, align 4
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78 %tmp12 = fadd float %tmp9, %tmp11
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79 %tmp13 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
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80 %tmp14 = load float, float addrspace(3)* %tmp13, align 4
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81 %tmp15 = fadd float %tmp12, %tmp14
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82 %tmp16 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
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83 %tmp17 = load float, float addrspace(3)* %tmp16, align 4
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84 %tmp18 = fadd float %tmp15, %tmp17
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85 %tmp19 = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
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86 %tmp20 = load float, float addrspace(3)* %tmp19, align 4
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87 %tmp21 = fadd float %tmp18, %tmp20
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88 %tmp22 = load float, float addrspace(3)* %arg, align 4
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89 %tmp23 = fadd float %tmp21, %tmp22
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90 store float %tmp23, float *%arg1, align 4
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91 ret void
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92 }
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93
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94 ; GCN-LABEL: ds_read32_combine_stride_8192:
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95 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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96 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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97 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:32
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98 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:64 offset1:96
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99 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:128 offset1:160
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100 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:192 offset1:224
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101 define amdgpu_kernel void @ds_read32_combine_stride_8192(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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102 bb:
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103 %tmp = load float, float addrspace(3)* %arg, align 4
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104 %tmp2 = fadd float %tmp, 0.000000e+00
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105 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2048
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106 %tmp4 = load float, float addrspace(3)* %tmp3, align 4
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107 %tmp5 = fadd float %tmp2, %tmp4
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108 %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4096
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109 %tmp7 = load float, float addrspace(3)* %tmp6, align 4
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110 %tmp8 = fadd float %tmp5, %tmp7
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111 %tmp9 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6144
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112 %tmp10 = load float, float addrspace(3)* %tmp9, align 4
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113 %tmp11 = fadd float %tmp8, %tmp10
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114 %tmp12 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8192
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115 %tmp13 = load float, float addrspace(3)* %tmp12, align 4
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116 %tmp14 = fadd float %tmp11, %tmp13
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117 %tmp15 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10240
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118 %tmp16 = load float, float addrspace(3)* %tmp15, align 4
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119 %tmp17 = fadd float %tmp14, %tmp16
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120 %tmp18 = getelementptr inbounds float, float addrspace(3)* %arg, i32 12288
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121 %tmp19 = load float, float addrspace(3)* %tmp18, align 4
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122 %tmp20 = fadd float %tmp17, %tmp19
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123 %tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 14336
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124 %tmp22 = load float, float addrspace(3)* %tmp21, align 4
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125 %tmp23 = fadd float %tmp20, %tmp22
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126 store float %tmp23, float *%arg1, align 4
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127 ret void
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128 }
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129
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130 ; GCN-LABEL: ds_read32_combine_stride_8192_shifted:
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131 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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132 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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133
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134 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
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135 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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136 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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137
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138 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
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139 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4008, [[BASE]]
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140 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8008, [[BASE]]
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141
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142 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
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143 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:32
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144 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:32
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145 define amdgpu_kernel void @ds_read32_combine_stride_8192_shifted(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
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146 bb:
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147 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2
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148 %tmp2 = load float, float addrspace(3)* %tmp, align 4
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149 %tmp3 = fadd float %tmp2, 0.000000e+00
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150 %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2050
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151 %tmp5 = load float, float addrspace(3)* %tmp4, align 4
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152 %tmp6 = fadd float %tmp3, %tmp5
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153 %tmp7 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4098
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154 %tmp8 = load float, float addrspace(3)* %tmp7, align 4
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155 %tmp9 = fadd float %tmp6, %tmp8
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156 %tmp10 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6146
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157 %tmp11 = load float, float addrspace(3)* %tmp10, align 4
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158 %tmp12 = fadd float %tmp9, %tmp11
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159 %tmp13 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8194
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160 %tmp14 = load float, float addrspace(3)* %tmp13, align 4
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161 %tmp15 = fadd float %tmp12, %tmp14
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162 %tmp16 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10242
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163 %tmp17 = load float, float addrspace(3)* %tmp16, align 4
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164 %tmp18 = fadd float %tmp15, %tmp17
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165 store float %tmp18, float *%arg1, align 4
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166 ret void
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167 }
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168
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169 ; GCN-LABEL: ds_read64_combine_stride_400:
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170 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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171 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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172
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173 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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174 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x960, [[BASE]]
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175
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176 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50
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177 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150
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178 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250
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179 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:50
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180 define amdgpu_kernel void @ds_read64_combine_stride_400(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
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181 bb:
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182 %tmp = load double, double addrspace(3)* %arg, align 8
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183 %tmp2 = fadd double %tmp, 0.000000e+00
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184 %tmp3 = getelementptr inbounds double, double addrspace(3)* %arg, i32 50
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185 %tmp4 = load double, double addrspace(3)* %tmp3, align 8
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186 %tmp5 = fadd double %tmp2, %tmp4
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187 %tmp6 = getelementptr inbounds double, double addrspace(3)* %arg, i32 100
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188 %tmp7 = load double, double addrspace(3)* %tmp6, align 8
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189 %tmp8 = fadd double %tmp5, %tmp7
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190 %tmp9 = getelementptr inbounds double, double addrspace(3)* %arg, i32 150
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191 %tmp10 = load double, double addrspace(3)* %tmp9, align 8
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192 %tmp11 = fadd double %tmp8, %tmp10
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193 %tmp12 = getelementptr inbounds double, double addrspace(3)* %arg, i32 200
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194 %tmp13 = load double, double addrspace(3)* %tmp12, align 8
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195 %tmp14 = fadd double %tmp11, %tmp13
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196 %tmp15 = getelementptr inbounds double, double addrspace(3)* %arg, i32 250
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197 %tmp16 = load double, double addrspace(3)* %tmp15, align 8
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198 %tmp17 = fadd double %tmp14, %tmp16
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199 %tmp18 = getelementptr inbounds double, double addrspace(3)* %arg, i32 300
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200 %tmp19 = load double, double addrspace(3)* %tmp18, align 8
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201 %tmp20 = fadd double %tmp17, %tmp19
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202 %tmp21 = getelementptr inbounds double, double addrspace(3)* %arg, i32 350
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203 %tmp22 = load double, double addrspace(3)* %tmp21, align 8
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204 %tmp23 = fadd double %tmp20, %tmp22
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205 store double %tmp23, double *%arg1, align 8
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206 ret void
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207 }
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208
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209 ; GCN-LABEL: ds_read64_combine_stride_8192_shifted:
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210 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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211 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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212
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213 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
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214 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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215 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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216
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217 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
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218 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4008, [[BASE]]
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219 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8008, [[BASE]]
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220
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221 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
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222 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:16
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223 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:16
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224 define amdgpu_kernel void @ds_read64_combine_stride_8192_shifted(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
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225 bb:
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226 %tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1
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227 %tmp2 = load double, double addrspace(3)* %tmp, align 8
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228 %tmp3 = fadd double %tmp2, 0.000000e+00
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229 %tmp4 = getelementptr inbounds double, double addrspace(3)* %arg, i32 1025
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230 %tmp5 = load double, double addrspace(3)* %tmp4, align 8
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231 %tmp6 = fadd double %tmp3, %tmp5
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232 %tmp7 = getelementptr inbounds double, double addrspace(3)* %arg, i32 2049
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233 %tmp8 = load double, double addrspace(3)* %tmp7, align 8
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234 %tmp9 = fadd double %tmp6, %tmp8
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235 %tmp10 = getelementptr inbounds double, double addrspace(3)* %arg, i32 3073
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236 %tmp11 = load double, double addrspace(3)* %tmp10, align 8
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237 %tmp12 = fadd double %tmp9, %tmp11
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238 %tmp13 = getelementptr inbounds double, double addrspace(3)* %arg, i32 4097
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239 %tmp14 = load double, double addrspace(3)* %tmp13, align 8
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240 %tmp15 = fadd double %tmp12, %tmp14
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241 %tmp16 = getelementptr inbounds double, double addrspace(3)* %arg, i32 5121
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242 %tmp17 = load double, double addrspace(3)* %tmp16, align 8
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243 %tmp18 = fadd double %tmp15, %tmp17
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244 store double %tmp18, double *%arg1, align 8
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245 ret void
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246 }
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247
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248 ; GCN-LABEL: ds_write32_combine_stride_400:
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249 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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250 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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251
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252 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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253 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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254 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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255
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256 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]]
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257 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]]
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258 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]]
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259
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260 ; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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261 ; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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262 ; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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263 ; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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264 define amdgpu_kernel void @ds_write32_combine_stride_400(float addrspace(3)* nocapture %arg) {
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265 bb:
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266 store float 1.000000e+00, float addrspace(3)* %arg, align 4
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267 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
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268 store float 1.000000e+00, float addrspace(3)* %tmp, align 4
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269 %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
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270 store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
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271 %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
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272 store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
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273 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
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274 store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
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275 %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
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276 store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
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277 %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
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278 store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
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279 %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
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280 store float 1.000000e+00, float addrspace(3)* %tmp6, align 4
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281 ret void
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282 }
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283
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284 ; GCN-LABEL: ds_write32_combine_stride_400_back:
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285 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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286 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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287
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288 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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289 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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290 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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291
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292 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]]
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293 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]]
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294 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]]
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295
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296 ; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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297 ; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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298 ; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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299 ; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
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300 define amdgpu_kernel void @ds_write32_combine_stride_400_back(float addrspace(3)* nocapture %arg) {
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301 bb:
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302 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
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303 store float 1.000000e+00, float addrspace(3)* %tmp, align 4
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304 %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
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305 store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
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306 %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
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307 store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
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308 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
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309 store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
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310 %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
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311 store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
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312 %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
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313 store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
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314 %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
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315 store float 1.000000e+00, float addrspace(3)* %tmp6, align 4
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316 store float 1.000000e+00, float addrspace(3)* %arg, align 4
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317 ret void
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318 }
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319
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320 ; GCN-LABEL: ds_write32_combine_stride_8192:
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321 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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322 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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323 ; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
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324 ; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:64 offset1:96
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325 ; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:128 offset1:160
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326 ; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:192 offset1:224
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327 define amdgpu_kernel void @ds_write32_combine_stride_8192(float addrspace(3)* nocapture %arg) {
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328 bb:
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329 store float 1.000000e+00, float addrspace(3)* %arg, align 4
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330 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2048
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331 store float 1.000000e+00, float addrspace(3)* %tmp, align 4
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332 %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4096
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333 store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
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334 %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6144
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335 store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
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336 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8192
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337 store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
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338 %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10240
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339 store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
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340 %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 12288
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341 store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
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342 %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 14336
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343 store float 1.000000e+00, float addrspace(3)* %tmp6, align 4
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344 ret void
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345 }
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346
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347 ; GCN-LABEL: ds_write32_combine_stride_8192_shifted:
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348 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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349 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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350
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351 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 4, [[BASE]]
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352 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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353 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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354
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355 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 4, [[BASE]]
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356 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4004, [[BASE]]
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357 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8004, [[BASE]]
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358
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359 ; GCN-DAG: ds_write2st64_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
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360 ; GCN-DAG: ds_write2st64_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
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361 ; GCN-DAG: ds_write2st64_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
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362 define amdgpu_kernel void @ds_write32_combine_stride_8192_shifted(float addrspace(3)* nocapture %arg) {
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363 bb:
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364 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 1
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365 store float 1.000000e+00, float addrspace(3)* %tmp, align 4
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366 %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2049
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367 store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
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368 %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4097
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369 store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
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370 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6145
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371 store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
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372 %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8193
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373 store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
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374 %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10241
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375 store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
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376 ret void
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|
|
377 }
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378
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379 ; GCN-LABEL: ds_write64_combine_stride_400:
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380 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
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381 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
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382
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383 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
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384 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x960, [[BASE]]
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385
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386 ; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
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387 ; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:100 offset1:150
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388 ; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:200 offset1:250
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389 ; GCN-DAG: ds_write2_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
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390 define amdgpu_kernel void @ds_write64_combine_stride_400(double addrspace(3)* nocapture %arg) {
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391 bb:
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|
392 store double 1.000000e+00, double addrspace(3)* %arg, align 8
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393 %tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 50
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394 store double 1.000000e+00, double addrspace(3)* %tmp, align 8
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395 %tmp1 = getelementptr inbounds double, double addrspace(3)* %arg, i32 100
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396 store double 1.000000e+00, double addrspace(3)* %tmp1, align 8
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397 %tmp2 = getelementptr inbounds double, double addrspace(3)* %arg, i32 150
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398 store double 1.000000e+00, double addrspace(3)* %tmp2, align 8
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399 %tmp3 = getelementptr inbounds double, double addrspace(3)* %arg, i32 200
|
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|
400 store double 1.000000e+00, double addrspace(3)* %tmp3, align 8
|
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|
401 %tmp4 = getelementptr inbounds double, double addrspace(3)* %arg, i32 250
|
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402 store double 1.000000e+00, double addrspace(3)* %tmp4, align 8
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403 %tmp5 = getelementptr inbounds double, double addrspace(3)* %arg, i32 300
|
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|
404 store double 1.000000e+00, double addrspace(3)* %tmp5, align 8
|
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|
405 %tmp6 = getelementptr inbounds double, double addrspace(3)* %arg, i32 350
|
|
|
406 store double 1.000000e+00, double addrspace(3)* %tmp6, align 8
|
|
|
407 ret void
|
|
|
408 }
|
|
|
409
|
|
|
410 ; GCN-LABEL: ds_write64_combine_stride_8192_shifted:
|
|
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411 ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
|
|
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412 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
|
|
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413
|
|
|
414 ; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
|
|
|
415 ; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
|
|
|
416 ; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
|
|
|
417
|
|
|
418 ; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
|
|
|
419 ; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4008, [[BASE]]
|
|
|
420 ; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8008, [[BASE]]
|
|
|
421
|
|
|
422 ; GCN-DAG: ds_write2st64_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
|
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|
423 ; GCN-DAG: ds_write2st64_b64 [[B2]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
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424 ; GCN-DAG: ds_write2st64_b64 [[B3]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
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|
425 define amdgpu_kernel void @ds_write64_combine_stride_8192_shifted(double addrspace(3)* nocapture %arg) {
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|
|
426 bb:
|
|
|
427 %tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1
|
|
|
428 store double 1.000000e+00, double addrspace(3)* %tmp, align 8
|
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|
429 %tmp1 = getelementptr inbounds double, double addrspace(3)* %arg, i32 1025
|
|
|
430 store double 1.000000e+00, double addrspace(3)* %tmp1, align 8
|
|
|
431 %tmp2 = getelementptr inbounds double, double addrspace(3)* %arg, i32 2049
|
|
|
432 store double 1.000000e+00, double addrspace(3)* %tmp2, align 8
|
|
|
433 %tmp3 = getelementptr inbounds double, double addrspace(3)* %arg, i32 3073
|
|
|
434 store double 1.000000e+00, double addrspace(3)* %tmp3, align 8
|
|
|
435 %tmp4 = getelementptr inbounds double, double addrspace(3)* %arg, i32 4097
|
|
|
436 store double 1.000000e+00, double addrspace(3)* %tmp4, align 8
|
|
|
437 %tmp5 = getelementptr inbounds double, double addrspace(3)* %arg, i32 5121
|
|
|
438 store double 1.000000e+00, double addrspace(3)* %tmp5, align 8
|
|
|
439 ret void
|
|
|
440 }
|
