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173
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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3
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4 @lds = internal addrspace(3) global [576 x double] undef, align 16
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5
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6 ; Stores to the same address appear multiple places in the same
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7 ; block. When sorted by offset, the merges would fail. We should form
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8 ; two groupings of ds_write2_b64 on either side of the fence.
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9 define amdgpu_kernel void @same_address_fence_merge_write2() #0 {
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10 ; GCN-LABEL: same_address_fence_merge_write2:
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11 ; GCN: ; %bb.0: ; %bb
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12 ; GCN-NEXT: s_mov_b32 s0, 0
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13 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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14 ; GCN-NEXT: s_mov_b32 s1, 0x40100000
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15 ; GCN-NEXT: v_mov_b32_e32 v0, s0
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16 ; GCN-NEXT: v_mov_b32_e32 v1, s1
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17 ; GCN-NEXT: v_add_u32_e32 v3, 0x840, v2
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18 ; GCN-NEXT: v_add_u32_e32 v4, 0xc60, v2
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19 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:66
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20 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:198
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21 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset1:66
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22 ; GCN-NEXT: ds_write2_b64 v4, v[0:1], v[0:1] offset1:66
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23 ; GCN-NEXT: s_mov_b32 s1, 0x3ff00000
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24 ; GCN-NEXT: v_mov_b32_e32 v0, s0
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25 ; GCN-NEXT: v_mov_b32_e32 v1, s1
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26 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
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27 ; GCN-NEXT: s_barrier
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28 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
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29 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:66
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30 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:198
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31 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset1:66
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32 ; GCN-NEXT: ds_write2_b64 v4, v[0:1], v[0:1] offset1:66
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33 ; GCN-NEXT: s_endpgm
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34 bb:
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35 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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36 %tmp1 = getelementptr inbounds [576 x double], [576 x double] addrspace(3)* @lds, i32 0, i32 %tmp
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37 store double 4.000000e+00, double addrspace(3)* %tmp1, align 8
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38 %tmp2 = getelementptr inbounds double, double addrspace(3)* %tmp1, i32 66
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39 store double 4.000000e+00, double addrspace(3)* %tmp2, align 8
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40 %tmp3 = getelementptr inbounds double, double addrspace(3)* %tmp1, i32 132
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41 store double 4.000000e+00, double addrspace(3)* %tmp3, align 8
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42 %tmp4 = getelementptr inbounds double, double addrspace(3)* %tmp1, i32 198
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43 store double 4.000000e+00, double addrspace(3)* %tmp4, align 8
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44 %tmp5 = getelementptr inbounds double, double addrspace(3)* %tmp1, i32 264
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45 store double 4.000000e+00, double addrspace(3)* %tmp5, align 8
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46 %tmp6 = getelementptr inbounds double, double addrspace(3)* %tmp1, i32 330
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47 store double 4.000000e+00, double addrspace(3)* %tmp6, align 8
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48 %tmp7 = getelementptr inbounds double, double addrspace(3)* %tmp1, i32 396
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49 store double 4.000000e+00, double addrspace(3)* %tmp7, align 8
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50 %tmp8 = getelementptr inbounds double, double addrspace(3)* %tmp1, i32 462
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51 store double 4.000000e+00, double addrspace(3)* %tmp8, align 8
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52 fence syncscope("workgroup") release
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53 tail call void @llvm.amdgcn.s.barrier()
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54 fence syncscope("workgroup") acquire
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55 store double 1.000000e+00, double addrspace(3)* %tmp1, align 8
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56 store double 1.000000e+00, double addrspace(3)* %tmp2, align 8
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57 store double 1.000000e+00, double addrspace(3)* %tmp3, align 8
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58 store double 1.000000e+00, double addrspace(3)* %tmp4, align 8
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59 store double 1.000000e+00, double addrspace(3)* %tmp5, align 8
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60 store double 1.000000e+00, double addrspace(3)* %tmp6, align 8
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61 store double 1.000000e+00, double addrspace(3)* %tmp7, align 8
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62 store double 1.000000e+00, double addrspace(3)* %tmp8, align 8
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63 ret void
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64 }
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65
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66 declare i32 @llvm.amdgcn.workitem.id.x() #0
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67 declare void @llvm.amdgcn.s.barrier() #1
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68
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69 attributes #0 = { nounwind readnone speculatable }
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70 attributes #1 = { convergent nounwind }
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71
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72 !0 = !{i32 0, i32 1024}
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