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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX906 -check-prefix=FUNC %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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4 ; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cedar -verify-machineinstrs < %s
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5 ; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=juniper -verify-machineinstrs < %s
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6 ; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s
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7 ; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=sumo -verify-machineinstrs < %s
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8 ; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=barts -verify-machineinstrs < %s
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9 ; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=caicos -verify-machineinstrs < %s
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10 ; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=turks -verify-machineinstrs < %s
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11
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12 declare float @llvm.fma.f32(float, float, float) nounwind readnone
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13 declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
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14 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
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15
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16 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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17
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18 ; FUNC-LABEL: {{^}}fma_f32:
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19 ; SI: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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20 ; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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21
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22 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}},
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23 ; EG: FMA {{\*? *}}[[RES]]
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24 define amdgpu_kernel void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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25 float addrspace(1)* %in2, float addrspace(1)* %in3) {
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26 %r0 = load float, float addrspace(1)* %in1
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27 %r1 = load float, float addrspace(1)* %in2
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28 %r2 = load float, float addrspace(1)* %in3
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29 %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
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30 store float %r3, float addrspace(1)* %out
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31 ret void
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32 }
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33
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34 ; GCN-LABEL: {{^}}fmac_to_3addr_f32:
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35 ; GCN: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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36 define float @fmac_to_3addr_f32(float %r0, float %r1, float %r2) {
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37 %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
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38 ret float %r3
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39 }
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40
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41 ; FUNC-LABEL: {{^}}fma_v2f32:
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42 ; SI: v_fma_f32
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43 ; SI: v_fma_f32
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44
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45 ; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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46 ; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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47
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48 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}},
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49 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]]
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50 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]
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51 define amdgpu_kernel void @fma_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
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52 <2 x float> addrspace(1)* %in2, <2 x float> addrspace(1)* %in3) {
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53 %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1
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54 %r1 = load <2 x float>, <2 x float> addrspace(1)* %in2
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55 %r2 = load <2 x float>, <2 x float> addrspace(1)* %in3
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56 %r3 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %r0, <2 x float> %r1, <2 x float> %r2)
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57 store <2 x float> %r3, <2 x float> addrspace(1)* %out
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58 ret void
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59 }
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60
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61 ; FUNC-LABEL: {{^}}fma_v4f32:
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62 ; SI: v_fma_f32
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63 ; SI: v_fma_f32
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64 ; SI: v_fma_f32
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65 ; SI: v_fma_f32
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66 ; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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67 ; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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68 ; GFX906: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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69 ; GFX906: v_fmac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+$}}
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70
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71 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}},
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72 ; EG-DAG: FMA {{\*? *}}[[RES]].X
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73 ; EG-DAG: FMA {{\*? *}}[[RES]].Y
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74 ; EG-DAG: FMA {{\*? *}}[[RES]].Z
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75 ; EG-DAG: FMA {{\*? *}}[[RES]].W
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76 define amdgpu_kernel void @fma_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
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77 <4 x float> addrspace(1)* %in2, <4 x float> addrspace(1)* %in3) {
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78 %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1
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79 %r1 = load <4 x float>, <4 x float> addrspace(1)* %in2
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80 %r2 = load <4 x float>, <4 x float> addrspace(1)* %in3
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81 %r3 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %r0, <4 x float> %r1, <4 x float> %r2)
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82 store <4 x float> %r3, <4 x float> addrspace(1)* %out
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83 ret void
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84 }
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85
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86 ; FUNC-LABEL: @fma_commute_mul_inline_imm_f32
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87 ; SI: v_fma_f32 {{v[0-9]+}}, {{v[0-9]+}}, 2.0, {{v[0-9]+}}
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88 define amdgpu_kernel void @fma_commute_mul_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
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89 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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90 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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91 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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92 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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93
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94 %a = load float, float addrspace(1)* %in.a.gep, align 4
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95 %b = load float, float addrspace(1)* %in.b.gep, align 4
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96
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97 %fma = call float @llvm.fma.f32(float %a, float 2.0, float %b)
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98 store float %fma, float addrspace(1)* %out.gep, align 4
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99 ret void
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100 }
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101
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102 ; FUNC-LABEL: @fma_commute_mul_s_f32
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103 define amdgpu_kernel void @fma_commute_mul_s_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b, float %b) nounwind {
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104 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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105 %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
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106 %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
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107 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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108
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109 %a = load float, float addrspace(1)* %in.a.gep, align 4
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110 %c = load float, float addrspace(1)* %in.b.gep, align 4
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111
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112 %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
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113 store float %fma, float addrspace(1)* %out.gep, align 4
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114 ret void
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115 }
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116
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117 ; Without special casing the inline constant check for v_fmac_f32's
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118 ; src2, this fails to fold the 1.0 into an fma.
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119
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120 ; FUNC-LABEL: {{^}}fold_inline_imm_into_fmac_src2_f32:
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121 ; GFX906: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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122 ; GFX906: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
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123
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124 ; GFX906: v_add_f32_e32 [[TMP2:v[0-9]+]], [[A]], [[A]]
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125 ; GFX906: v_fma_f32 v{{[0-9]+}}, [[TMP2]], -4.0, 1.0
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126 define amdgpu_kernel void @fold_inline_imm_into_fmac_src2_f32(float addrspace(1)* %out, float addrspace(1)* %a, float addrspace(1)* %b) nounwind {
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127 bb:
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128 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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129 %tid.ext = sext i32 %tid to i64
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130 %gep.a = getelementptr inbounds float, float addrspace(1)* %a, i64 %tid.ext
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131 %gep.b = getelementptr inbounds float, float addrspace(1)* %b, i64 %tid.ext
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132 %gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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133 %tmp = load volatile float, float addrspace(1)* %gep.a
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134 %tmp1 = load volatile float, float addrspace(1)* %gep.b
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135 %tmp2 = fadd contract float %tmp, %tmp
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136 %tmp3 = fmul contract float %tmp2, 4.0
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137 %tmp4 = fsub contract float 1.0, %tmp3
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138 %tmp5 = fadd contract float %tmp4, %tmp1
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139 %tmp6 = fadd contract float %tmp1, %tmp1
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140 %tmp7 = fmul contract float %tmp6, %tmp
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141 %tmp8 = fsub contract float 1.0, %tmp7
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142 %tmp9 = fmul contract float %tmp8, 8.0
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143 %tmp10 = fadd contract float %tmp5, %tmp9
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144 store float %tmp10, float addrspace(1)* %gep.out
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145 ret void
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146 }
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