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1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=R600 -check-prefix=FUNC %s
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4
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5 ; FUNC-LABEL: {{^}}s_fneg_f32:
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6 ; R600: -PV
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7
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8 ; GCN: s_load_dword [[VAL:s[0-9]+]]
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9 ; GCN: s_xor_b32 [[NEG_VAL:s[0-9]+]], [[VAL]], 0x80000000
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10 ; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[NEG_VAL]]
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11 define amdgpu_kernel void @s_fneg_f32(float addrspace(1)* %out, float %in) {
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12 %fneg = fsub float -0.000000e+00, %in
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13 store float %fneg, float addrspace(1)* %out
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14 ret void
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15 }
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16
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17 ; FUNC-LABEL: {{^}}s_fneg_v2f32:
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18 ; R600: -PV
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19 ; R600: -PV
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20
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21 ; GCN: s_brev_b32 [[SIGNBIT:s[0-9]+]], 1
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22 ; GCN: s_xor_b32
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23 ; GCN: s_xor_b32
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24 define amdgpu_kernel void @s_fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
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25 %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
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26 store <2 x float> %fneg, <2 x float> addrspace(1)* %out
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27 ret void
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28 }
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29
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30 ; FUNC-LABEL: {{^}}s_fneg_v4f32:
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31 ; R600: -PV
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32 ; R600: -T
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33 ; R600: -PV
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34 ; R600: -PV
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35
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36 ; GCN: s_xor_b32
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37 ; GCN: s_xor_b32
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38 ; GCN: s_xor_b32
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39 ; GCN: s_xor_b32
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40 define amdgpu_kernel void @s_fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
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41 %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
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42 store <4 x float> %fneg, <4 x float> addrspace(1)* %out
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43 ret void
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44 }
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45
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46 ; DAGCombiner will transform:
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47 ; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
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48 ; unless the target returns true for isNegFree()
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49
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50 ; FUNC-LABEL: {{^}}fsub0_f32:
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51
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52 ; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}}
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53
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54 ; R600-NOT: XOR
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55 ; R600: -KC0[2].Z
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56 define amdgpu_kernel void @fsub0_f32(float addrspace(1)* %out, i32 %in) {
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57 %bc = bitcast i32 %in to float
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58 %fsub = fsub float 0.0, %bc
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59 store float %fsub, float addrspace(1)* %out
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60 ret void
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61 }
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62 ; FUNC-LABEL: {{^}}fneg_free_f32:
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63 ; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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64 ; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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65
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66 ; GCN: s_xor_b32 [[RES:s[0-9]+]], [[NEG_VALUE]], 0x80000000
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67 ; GCN: v_mov_b32_e32 [[V_RES:v[0-9]+]], [[RES]]
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68 ; GCN: buffer_store_dword [[V_RES]]
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69
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70 ; R600-NOT: XOR
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71 ; R600: -PV.W
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72 define amdgpu_kernel void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
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73 %bc = bitcast i32 %in to float
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74 %fsub = fsub float -0.0, %bc
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75 store float %fsub, float addrspace(1)* %out
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76 ret void
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77 }
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78
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79 ; FUNC-LABEL: {{^}}fneg_fold_f32:
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80 ; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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81 ; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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82 ; GCN-NOT: xor
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83 ; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
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84 define amdgpu_kernel void @fneg_fold_f32(float addrspace(1)* %out, float %in) {
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85 %fsub = fsub float -0.0, %in
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86 %fmul = fmul float %fsub, %in
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87 store float %fmul, float addrspace(1)* %out
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88 ret void
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89 }
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90
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91 ; Make sure we turn some integer operations back into fabs
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92 ; FUNC-LABEL: {{^}}bitpreserve_fneg_f32:
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93 ; GCN: v_mul_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -4.0
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94 define amdgpu_kernel void @bitpreserve_fneg_f32(float addrspace(1)* %out, float %in) {
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95 %in.bc = bitcast float %in to i32
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96 %int.abs = xor i32 %in.bc, 2147483648
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97 %bc = bitcast i32 %int.abs to float
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98 %fadd = fmul float %bc, 4.0
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99 store float %fadd, float addrspace(1)* %out
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100 ret void
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101 }
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