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150
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,IDXMODE,GFX9 %s
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2
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3 ; indexing of vectors.
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4
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5 ; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll
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6 ; to avoid gfx9 scheduling induced issues.
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7
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8
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9 ; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block:
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10 ; GCN-DAG: s_load_dwordx16 s{{\[}}[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]{{\]}}
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11 ; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]]
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12 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
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13
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14 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]]
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15 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
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16
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173
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17 ; GCN: v_cmp_eq_u32_e32
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18 ; GCN-COUNT-32: v_cndmask_b32
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150
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19
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173
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20 ; GCN-COUNT-4: buffer_store_dwordx4
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150
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21 define amdgpu_kernel void @insert_vgpr_offset_multiple_in_block(<16 x i32> addrspace(1)* %out0, <16 x i32> addrspace(1)* %out1, i32 addrspace(1)* %in, <16 x i32> %vec0) #0 {
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22 entry:
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23 %id = call i32 @llvm.amdgcn.workitem.id.x() #1
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24 %id.ext = zext i32 %id to i64
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25 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %id.ext
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26 %idx0 = load volatile i32, i32 addrspace(1)* %gep
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27 %idx1 = add i32 %idx0, 1
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28 %live.out.val = call i32 asm sideeffect "v_mov_b32 $0, 62", "=v"()
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29 %vec1 = insertelement <16 x i32> %vec0, i32 %live.out.val, i32 %idx0
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30 %vec2 = insertelement <16 x i32> %vec1, i32 63, i32 %idx1
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31 store volatile <16 x i32> %vec2, <16 x i32> addrspace(1)* %out0
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32 %cmp = icmp eq i32 %id, 0
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33 br i1 %cmp, label %bb1, label %bb2
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34
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35 bb1:
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36 store volatile i32 %live.out.val, i32 addrspace(1)* undef
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37 br label %bb2
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38
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39 bb2:
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40 ret void
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41 }
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42
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43 declare i32 @llvm.amdgcn.workitem.id.x() #1
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44 declare void @llvm.amdgcn.s.barrier() #2
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45
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46 attributes #0 = { nounwind }
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47 attributes #1 = { nounwind readnone }
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48 attributes #2 = { nounwind convergent }
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