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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
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2
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3 declare i1 @llvm.amdgcn.class.f32(float, i32) #1
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4 declare i1 @llvm.amdgcn.class.f64(double, i32) #1
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5 declare i32 @llvm.amdgcn.workitem.id.x() #1
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6 declare float @llvm.fabs.f32(float) #1
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7 declare double @llvm.fabs.f64(double) #1
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8
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9 ; SI-LABEL: {{^}}test_class_f32:
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10 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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11 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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12 ; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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13 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[VB]]
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14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
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15 ; SI-NEXT: buffer_store_dword [[RESULT]]
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16 ; SI: s_endpgm
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17 define amdgpu_kernel void @test_class_f32(i32 addrspace(1)* %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {
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18 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 %b) #1
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19 %sext = sext i1 %result to i32
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20 store i32 %sext, i32 addrspace(1)* %out, align 4
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21 ret void
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22 }
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23
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24 ; SI-LABEL: {{^}}test_class_fabs_f32:
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25 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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26 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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27 ; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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28 ; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]]
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29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
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30 ; SI-NEXT: buffer_store_dword [[RESULT]]
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31 ; SI: s_endpgm
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32 define amdgpu_kernel void @test_class_fabs_f32(i32 addrspace(1)* %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {
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33 %a.fabs = call float @llvm.fabs.f32(float %a) #1
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34 %result = call i1 @llvm.amdgcn.class.f32(float %a.fabs, i32 %b) #1
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35 %sext = sext i1 %result to i32
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36 store i32 %sext, i32 addrspace(1)* %out, align 4
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37 ret void
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38 }
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39
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40 ; SI-LABEL: {{^}}test_class_fneg_f32:
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41 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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42 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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43 ; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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44 ; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]]
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45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
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46 ; SI-NEXT: buffer_store_dword [[RESULT]]
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47 ; SI: s_endpgm
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48 define amdgpu_kernel void @test_class_fneg_f32(i32 addrspace(1)* %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {
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49 %a.fneg = fsub float -0.0, %a
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50 %result = call i1 @llvm.amdgcn.class.f32(float %a.fneg, i32 %b) #1
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51 %sext = sext i1 %result to i32
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52 store i32 %sext, i32 addrspace(1)* %out, align 4
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53 ret void
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54 }
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55
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56 ; SI-LABEL: {{^}}test_class_fneg_fabs_f32:
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57 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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58 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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59 ; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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60 ; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]]
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61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
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62 ; SI-NEXT: buffer_store_dword [[RESULT]]
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63 ; SI: s_endpgm
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64 define amdgpu_kernel void @test_class_fneg_fabs_f32(i32 addrspace(1)* %out, [8 x i32], float %a, [8 x i32], i32 %b) #0 {
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65 %a.fabs = call float @llvm.fabs.f32(float %a) #1
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66 %a.fneg.fabs = fsub float -0.0, %a.fabs
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67 %result = call i1 @llvm.amdgcn.class.f32(float %a.fneg.fabs, i32 %b) #1
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68 %sext = sext i1 %result to i32
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69 store i32 %sext, i32 addrspace(1)* %out, align 4
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70 ret void
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71 }
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72
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73 ; SI-LABEL: {{^}}test_class_1_f32:
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74 ; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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75 ; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 1{{$}}
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76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
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77 ; SI-NEXT: buffer_store_dword [[RESULT]]
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78 ; SI: s_endpgm
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79 define amdgpu_kernel void @test_class_1_f32(i32 addrspace(1)* %out, float %a) #0 {
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80 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1
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81 %sext = sext i1 %result to i32
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82 store i32 %sext, i32 addrspace(1)* %out, align 4
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83 ret void
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84 }
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85
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86 ; SI-LABEL: {{^}}test_class_64_f32:
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87 ; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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88 ; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 64{{$}}
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89 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
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90 ; SI-NEXT: buffer_store_dword [[RESULT]]
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91 ; SI: s_endpgm
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92 define amdgpu_kernel void @test_class_64_f32(i32 addrspace(1)* %out, float %a) #0 {
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93 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 64) #1
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94 %sext = sext i1 %result to i32
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95 store i32 %sext, i32 addrspace(1)* %out, align 4
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96 ret void
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97 }
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98
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99 ; Set all 10 bits of mask
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100 ; SI-LABEL: {{^}}test_class_full_mask_f32:
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101 ; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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102 ; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}}
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103 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
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104 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
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105 ; SI-NEXT: buffer_store_dword [[RESULT]]
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106 ; SI: s_endpgm
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107 define amdgpu_kernel void @test_class_full_mask_f32(i32 addrspace(1)* %out, float %a) #0 {
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108 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 1023) #1
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109 %sext = sext i1 %result to i32
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110 store i32 %sext, i32 addrspace(1)* %out, align 4
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111 ret void
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112 }
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113
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114 ; SI-LABEL: {{^}}test_class_9bit_mask_f32:
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115 ; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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116 ; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}}
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117 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]]
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118 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
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119 ; SI-NEXT: buffer_store_dword [[RESULT]]
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120 ; SI: s_endpgm
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121 define amdgpu_kernel void @test_class_9bit_mask_f32(i32 addrspace(1)* %out, float %a) #0 {
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122 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 511) #1
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123 %sext = sext i1 %result to i32
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124 store i32 %sext, i32 addrspace(1)* %out, align 4
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125 ret void
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126 }
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127
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128 ; SI-LABEL: {{^}}v_test_class_full_mask_f32:
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129 ; SI-DAG: buffer_load_dword [[VA:v[0-9]+]]
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130 ; SI-DAG: s_movk_i32 [[MASK:s[0-9]+]], 0x1ff{{$}}
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131 ; SI: v_cmp_class_f32_e64 s[{{[0-9]}}:{{[0-9]}}], [[VA]], [[MASK]]
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132 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, s[{{[0-9]}}:{{[0-9]}}]
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133 ; SI: buffer_store_dword [[RESULT]]
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134 ; SI: s_endpgm
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135 define amdgpu_kernel void @v_test_class_full_mask_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
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136 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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137 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
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138 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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139 %a = load float, float addrspace(1)* %gep.in
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140
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141 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 511) #1
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142 %sext = sext i1 %result to i32
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143 store i32 %sext, i32 addrspace(1)* %gep.out, align 4
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144 ret void
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145 }
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146
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147 ; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f32:
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148 ; SI-DAG: buffer_load_dword [[VB:v[0-9]+]]
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149 ; SI: v_cmp_class_f32_e32 vcc, 1.0, [[VB]]
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150 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
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151 ; SI: buffer_store_dword [[RESULT]]
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152 ; SI: s_endpgm
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153 define amdgpu_kernel void @test_class_inline_imm_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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154 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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155 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
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156 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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157 %b = load i32, i32 addrspace(1)* %gep.in
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158
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159 %result = call i1 @llvm.amdgcn.class.f32(float 1.0, i32 %b) #1
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160 %sext = sext i1 %result to i32
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161 store i32 %sext, i32 addrspace(1)* %gep.out, align 4
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162 ret void
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163 }
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164
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165 ; FIXME: Why isn't this using a literal constant operand?
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166 ; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f32:
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167 ; SI-DAG: buffer_load_dword [[VB:v[0-9]+]]
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168 ; SI-DAG: s_mov_b32 [[VK:s[0-9]+]], 0x44800000
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169 ; SI: v_cmp_class_f32_e32 vcc, [[VK]], [[VB]]
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170 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
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171 ; SI: buffer_store_dword [[RESULT]]
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172 ; SI: s_endpgm
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173 define amdgpu_kernel void @test_class_lit_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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174 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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175 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
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176 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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177 %b = load i32, i32 addrspace(1)* %gep.in
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178
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179 %result = call i1 @llvm.amdgcn.class.f32(float 1024.0, i32 %b) #1
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180 %sext = sext i1 %result to i32
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181 store i32 %sext, i32 addrspace(1)* %gep.out, align 4
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182 ret void
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183 }
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184
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185 ; SI-LABEL: {{^}}test_class_f64:
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186 ; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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187 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1d
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188 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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189 ; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[VB]]
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190 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
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191 ; SI-NEXT: buffer_store_dword [[RESULT]]
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192 ; SI: s_endpgm
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193 define amdgpu_kernel void @test_class_f64(i32 addrspace(1)* %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {
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194 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 %b) #1
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195 %sext = sext i1 %result to i32
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196 store i32 %sext, i32 addrspace(1)* %out, align 4
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197 ret void
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198 }
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199
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200 ; SI-LABEL: {{^}}test_class_fabs_f64:
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201 ; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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202 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1d
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203 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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204 ; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]]
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205 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
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206 ; SI-NEXT: buffer_store_dword [[RESULT]]
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207 ; SI: s_endpgm
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208 define amdgpu_kernel void @test_class_fabs_f64(i32 addrspace(1)* %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {
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209 %a.fabs = call double @llvm.fabs.f64(double %a) #1
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210 %result = call i1 @llvm.amdgcn.class.f64(double %a.fabs, i32 %b) #1
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211 %sext = sext i1 %result to i32
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212 store i32 %sext, i32 addrspace(1)* %out, align 4
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213 ret void
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214 }
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215
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216 ; SI-LABEL: {{^}}test_class_fneg_f64:
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217 ; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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218 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1d
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219 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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220 ; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]]
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221 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
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222 ; SI-NEXT: buffer_store_dword [[RESULT]]
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223 ; SI: s_endpgm
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224 define amdgpu_kernel void @test_class_fneg_f64(i32 addrspace(1)* %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {
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225 %a.fneg = fsub double -0.0, %a
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226 %result = call i1 @llvm.amdgcn.class.f64(double %a.fneg, i32 %b) #1
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227 %sext = sext i1 %result to i32
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228 store i32 %sext, i32 addrspace(1)* %out, align 4
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229 ret void
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230 }
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231
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232 ; SI-LABEL: {{^}}test_class_fneg_fabs_f64:
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233 ; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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234 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1d
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235 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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236 ; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]]
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237 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
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238 ; SI-NEXT: buffer_store_dword [[RESULT]]
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239 ; SI: s_endpgm
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240 define amdgpu_kernel void @test_class_fneg_fabs_f64(i32 addrspace(1)* %out, [8 x i32], double %a, [8 x i32], i32 %b) #0 {
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241 %a.fabs = call double @llvm.fabs.f64(double %a) #1
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242 %a.fneg.fabs = fsub double -0.0, %a.fabs
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243 %result = call i1 @llvm.amdgcn.class.f64(double %a.fneg.fabs, i32 %b) #1
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244 %sext = sext i1 %result to i32
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245 store i32 %sext, i32 addrspace(1)* %out, align 4
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246 ret void
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247 }
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248
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249 ; SI-LABEL: {{^}}test_class_1_f64:
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250 ; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 1{{$}}
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|
251 ; SI: s_endpgm
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|
|
252 define amdgpu_kernel void @test_class_1_f64(i32 addrspace(1)* %out, double %a) #0 {
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|
|
253 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 1) #1
|
|
|
254 %sext = sext i1 %result to i32
|
|
|
255 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
256 ret void
|
|
|
257 }
|
|
|
258
|
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|
259 ; SI-LABEL: {{^}}test_class_64_f64:
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260 ; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 64{{$}}
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|
261 ; SI: s_endpgm
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|
|
262 define amdgpu_kernel void @test_class_64_f64(i32 addrspace(1)* %out, double %a) #0 {
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|
|
263 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 64) #1
|
|
|
264 %sext = sext i1 %result to i32
|
|
|
265 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
266 ret void
|
|
|
267 }
|
|
|
268
|
|
|
269 ; Set all 9 bits of mask
|
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|
270 ; SI-LABEL: {{^}}test_class_full_mask_f64:
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|
271 ; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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272 ; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}}
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273 ; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[MASK]]
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274 ; SI-NOT: vcc
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275 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
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276 ; SI-NEXT: buffer_store_dword [[RESULT]]
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277 ; SI: s_endpgm
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278 define amdgpu_kernel void @test_class_full_mask_f64(i32 addrspace(1)* %out, [8 x i32], double %a) #0 {
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279 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 511) #1
|
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280 %sext = sext i1 %result to i32
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|
281 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
282 ret void
|
|
|
283 }
|
|
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284
|
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|
285 ; SI-LABEL: {{^}}v_test_class_full_mask_f64:
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|
286 ; SI-DAG: buffer_load_dwordx2 [[VA:v\[[0-9]+:[0-9]+\]]]
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287 ; SI-DAG: s_movk_i32 [[MASK:s[0-9]+]], 0x1ff{{$}}
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|
288 ; SI: v_cmp_class_f64_e64 s[{{[0-9]}}:{{[0-9]}}], [[VA]], [[MASK]]
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|
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289 ; SI-NOT: vcc
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|
290 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, s[{{[0-9]}}:{{[0-9]}}]
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|
|
291 ; SI: buffer_store_dword [[RESULT]]
|
|
|
292 ; SI: s_endpgm
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|
|
293 define amdgpu_kernel void @v_test_class_full_mask_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #0 {
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|
|
294 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
295 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid
|
|
|
296 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
297 %a = load double, double addrspace(1)* %in
|
|
|
298
|
|
|
299 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 511) #1
|
|
|
300 %sext = sext i1 %result to i32
|
|
|
301 store i32 %sext, i32 addrspace(1)* %gep.out, align 4
|
|
|
302 ret void
|
|
|
303 }
|
|
|
304
|
|
|
305 ; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f64:
|
|
|
306 ; XSI: v_cmp_class_f64_e32 vcc, 1.0,
|
|
|
307 ; SI: v_cmp_class_f64_e32 vcc,
|
|
|
308 ; SI: s_endpgm
|
|
|
309 define amdgpu_kernel void @test_class_inline_imm_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
|
|
310 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
311 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
|
|
|
312 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
313 %b = load i32, i32 addrspace(1)* %gep.in
|
|
|
314
|
|
|
315 %result = call i1 @llvm.amdgcn.class.f64(double 1.0, i32 %b) #1
|
|
|
316 %sext = sext i1 %result to i32
|
|
|
317 store i32 %sext, i32 addrspace(1)* %gep.out, align 4
|
|
|
318 ret void
|
|
|
319 }
|
|
|
320
|
|
|
321 ; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f64:
|
|
|
322 ; SI: v_cmp_class_f64_e32 vcc, s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
|
|
|
323 ; SI: s_endpgm
|
|
|
324 define amdgpu_kernel void @test_class_lit_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
|
|
325 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
326 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid
|
|
|
327 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
328 %b = load i32, i32 addrspace(1)* %gep.in
|
|
|
329
|
|
|
330 %result = call i1 @llvm.amdgcn.class.f64(double 1024.0, i32 %b) #1
|
|
|
331 %sext = sext i1 %result to i32
|
|
|
332 store i32 %sext, i32 addrspace(1)* %gep.out, align 4
|
|
|
333 ret void
|
|
|
334 }
|
|
|
335
|
|
|
336 ; SI-LABEL: {{^}}test_fold_or_class_f32_0:
|
|
|
337 ; SI-NOT: v_cmp_class
|
|
|
338 ; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 3{{$}}
|
|
|
339 ; SI-NOT: v_cmp_class
|
|
|
340 ; SI: s_endpgm
|
|
|
341 define amdgpu_kernel void @test_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
|
342 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
343 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
344 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
345 %a = load float, float addrspace(1)* %gep.in
|
|
|
346
|
|
|
347 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1
|
|
|
348 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 3) #1
|
|
|
349 %or = or i1 %class0, %class1
|
|
|
350
|
|
|
351 %sext = sext i1 %or to i32
|
|
|
352 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
353 ret void
|
|
|
354 }
|
|
|
355
|
|
|
356 ; SI-LABEL: {{^}}test_fold_or3_class_f32_0:
|
|
|
357 ; SI-NOT: v_cmp_class
|
|
|
358 ; SI: v_cmp_class_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}}
|
|
|
359 ; SI-NOT: v_cmp_class
|
|
|
360 ; SI: s_endpgm
|
|
|
361 define amdgpu_kernel void @test_fold_or3_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
|
362 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
363 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
364 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
365 %a = load float, float addrspace(1)* %gep.in
|
|
|
366
|
|
|
367 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1
|
|
|
368 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 2) #1
|
|
|
369 %class2 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1
|
|
|
370 %or.0 = or i1 %class0, %class1
|
|
|
371 %or.1 = or i1 %or.0, %class2
|
|
|
372
|
|
|
373 %sext = sext i1 %or.1 to i32
|
|
|
374 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
375 ret void
|
|
|
376 }
|
|
|
377
|
|
|
378 ; SI-LABEL: {{^}}test_fold_or_all_tests_class_f32_0:
|
|
|
379 ; SI-NOT: v_cmp_class
|
|
|
380 ; SI: s_movk_i32 [[MASK:s[0-9]+]], 0x3ff{{$}}
|
|
|
381 ; SI: v_cmp_class_f32_e64 s[0:1], v{{[0-9]+}}, [[MASK]]{{$}}
|
|
|
382 ; SI-NOT: v_cmp_class
|
|
|
383 ; SI: s_endpgm
|
|
|
384 define amdgpu_kernel void @test_fold_or_all_tests_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
|
385 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
386 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
387 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
388 %a = load float, float addrspace(1)* %gep.in
|
|
|
389
|
|
|
390 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1
|
|
|
391 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 2) #1
|
|
|
392 %class2 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1
|
|
|
393 %class3 = call i1 @llvm.amdgcn.class.f32(float %a, i32 8) #1
|
|
|
394 %class4 = call i1 @llvm.amdgcn.class.f32(float %a, i32 16) #1
|
|
|
395 %class5 = call i1 @llvm.amdgcn.class.f32(float %a, i32 32) #1
|
|
|
396 %class6 = call i1 @llvm.amdgcn.class.f32(float %a, i32 64) #1
|
|
|
397 %class7 = call i1 @llvm.amdgcn.class.f32(float %a, i32 128) #1
|
|
|
398 %class8 = call i1 @llvm.amdgcn.class.f32(float %a, i32 256) #1
|
|
|
399 %class9 = call i1 @llvm.amdgcn.class.f32(float %a, i32 512) #1
|
|
|
400 %or.0 = or i1 %class0, %class1
|
|
|
401 %or.1 = or i1 %or.0, %class2
|
|
|
402 %or.2 = or i1 %or.1, %class3
|
|
|
403 %or.3 = or i1 %or.2, %class4
|
|
|
404 %or.4 = or i1 %or.3, %class5
|
|
|
405 %or.5 = or i1 %or.4, %class6
|
|
|
406 %or.6 = or i1 %or.5, %class7
|
|
|
407 %or.7 = or i1 %or.6, %class8
|
|
|
408 %or.8 = or i1 %or.7, %class9
|
|
|
409 %sext = sext i1 %or.8 to i32
|
|
|
410 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
411 ret void
|
|
|
412 }
|
|
|
413
|
|
|
414 ; SI-LABEL: {{^}}test_fold_or_class_f32_1:
|
|
|
415 ; SI-NOT: v_cmp_class
|
|
|
416 ; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 12{{$}}
|
|
|
417 ; SI-NOT: v_cmp_class
|
|
|
418 ; SI: s_endpgm
|
|
|
419 define amdgpu_kernel void @test_fold_or_class_f32_1(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
|
420 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
421 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
422 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
423 %a = load float, float addrspace(1)* %gep.in
|
|
|
424
|
|
|
425 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1
|
|
|
426 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 8) #1
|
|
|
427 %or = or i1 %class0, %class1
|
|
|
428
|
|
|
429 %sext = sext i1 %or to i32
|
|
|
430 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
431 ret void
|
|
|
432 }
|
|
|
433
|
|
|
434 ; SI-LABEL: {{^}}test_fold_or_class_f32_2:
|
|
|
435 ; SI-NOT: v_cmp_class
|
|
|
436 ; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}}
|
|
|
437 ; SI-NOT: v_cmp_class
|
|
|
438 ; SI: s_endpgm
|
|
|
439 define amdgpu_kernel void @test_fold_or_class_f32_2(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
|
440 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
441 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
442 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
443 %a = load float, float addrspace(1)* %gep.in
|
|
|
444
|
|
|
445 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 7) #1
|
|
|
446 %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 7) #1
|
|
|
447 %or = or i1 %class0, %class1
|
|
|
448
|
|
|
449 %sext = sext i1 %or to i32
|
|
|
450 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
451 ret void
|
|
|
452 }
|
|
|
453
|
|
|
454 ; SI-LABEL: {{^}}test_no_fold_or_class_f32_0:
|
|
|
455 ; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 4{{$}}
|
|
|
456 ; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 8{{$}}
|
|
|
457 ; SI: s_or_b64
|
|
|
458 ; SI: s_endpgm
|
|
|
459 define amdgpu_kernel void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in, float %b) #0 {
|
|
|
460 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
461 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
462 %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
463 %a = load float, float addrspace(1)* %gep.in
|
|
|
464
|
|
|
465 %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1
|
|
|
466 %class1 = call i1 @llvm.amdgcn.class.f32(float %b, i32 8) #1
|
|
|
467 %or = or i1 %class0, %class1
|
|
|
468
|
|
|
469 %sext = sext i1 %or to i32
|
|
|
470 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
471 ret void
|
|
|
472 }
|
|
|
473
|
|
|
474 ; SI-LABEL: {{^}}test_class_0_f32:
|
|
|
475 ; SI-NOT: v_cmp_class
|
|
|
476 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
|
|
|
477 ; SI: buffer_store_dword [[RESULT]]
|
|
|
478 ; SI: s_endpgm
|
|
|
479 define amdgpu_kernel void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 {
|
|
|
480 %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 0) #1
|
|
|
481 %sext = sext i1 %result to i32
|
|
|
482 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
483 ret void
|
|
|
484 }
|
|
|
485
|
|
|
486 ; SI-LABEL: {{^}}test_class_0_f64:
|
|
|
487 ; SI-NOT: v_cmp_class
|
|
|
488 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
|
|
|
489 ; SI: buffer_store_dword [[RESULT]]
|
|
|
490 ; SI: s_endpgm
|
|
|
491 define amdgpu_kernel void @test_class_0_f64(i32 addrspace(1)* %out, double %a) #0 {
|
|
|
492 %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 0) #1
|
|
|
493 %sext = sext i1 %result to i32
|
|
|
494 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
495 ret void
|
|
|
496 }
|
|
|
497
|
|
|
498 ; FIXME: Why is the extension still here?
|
|
|
499 ; SI-LABEL: {{^}}test_class_undef_f32:
|
|
|
500 ; SI-NOT: v_cmp_class
|
|
|
501 ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, -1,
|
|
|
502 ; SI: buffer_store_dword
|
|
|
503 define amdgpu_kernel void @test_class_undef_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 {
|
|
|
504 %result = call i1 @llvm.amdgcn.class.f32(float undef, i32 %b) #1
|
|
|
505 %sext = sext i1 %result to i32
|
|
|
506 store i32 %sext, i32 addrspace(1)* %out, align 4
|
|
|
507 ret void
|
|
|
508 }
|
|
|
509
|
|
|
510 ; SI-LABEL: {{^}}test_fold_and_ord:
|
|
|
511 ; SI: s_waitcnt
|
|
|
512 ; SI-NEXT: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v0, 32{{$}}
|
|
|
513 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, [[COND]]
|
|
|
514 ; SI-NEXT: s_setpc_b64
|
|
|
515 define i1 @test_fold_and_ord(float %a) {
|
|
|
516 %class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1
|
|
|
517 %ord = fcmp ord float %a, %a
|
|
|
518 %and = and i1 %ord, %class
|
|
|
519 ret i1 %and
|
|
|
520 }
|
|
|
521
|
|
|
522 ; SI-LABEL: {{^}}test_fold_and_unord:
|
|
|
523 ; SI: s_waitcnt
|
|
|
524 ; SI-NEXT: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v0, 3{{$}}
|
|
|
525 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, [[COND]]
|
|
|
526 ; SI-NEXT: s_setpc_b64
|
|
|
527 define i1 @test_fold_and_unord(float %a) {
|
|
|
528 %class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1
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529 %ord = fcmp uno float %a, %a
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530 %and = and i1 %ord, %class
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531 ret i1 %and
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532 }
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533
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534 ; SI-LABEL: {{^}}test_fold_and_ord_multi_use:
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535 ; SI: v_cmp_class
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536 ; SI-NOT: v_cmp_class
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537 ; SI: v_cmp_o
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538 ; SI: s_and_b64
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539 define i1 @test_fold_and_ord_multi_use(float %a) {
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540 %class = call i1 @llvm.amdgcn.class.f32(float %a, i32 35) #1
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541 store volatile i1 %class, i1 addrspace(1)* undef
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542 %ord = fcmp ord float %a, %a
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543 %and = and i1 %ord, %class
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544 ret i1 %and
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545 }
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546
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547 attributes #0 = { nounwind }
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548 attributes #1 = { nounwind readnone }
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