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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,SI
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3 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,GFX89,VI
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4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,GFX89,GFX9
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5
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6 define amdgpu_kernel void @s_cvt_pkrtz_v2f16_f32(<2 x half> addrspace(1)* %out, float %x, float %y) #0 {
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7 ; SI-LABEL: s_cvt_pkrtz_v2f16_f32:
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8 ; SI: ; %bb.0:
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9 ; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
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10 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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11 ; SI-NEXT: s_mov_b32 s7, 0xf000
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12 ; SI-NEXT: s_mov_b32 s6, -1
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13 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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14 ; SI-NEXT: v_mov_b32_e32 v0, s3
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15 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, s2, v0
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16 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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17 ; SI-NEXT: s_endpgm
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18 ;
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19 ; VI-LABEL: s_cvt_pkrtz_v2f16_f32:
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20 ; VI: ; %bb.0:
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21 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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22 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
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23 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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173
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24 ; VI-NEXT: v_mov_b32_e32 v0, s1
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25 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v2, s0, v0
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150
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26 ; VI-NEXT: v_mov_b32_e32 v0, s2
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27 ; VI-NEXT: v_mov_b32_e32 v1, s3
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28 ; VI-NEXT: flat_store_dword v[0:1], v2
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29 ; VI-NEXT: s_endpgm
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30 ;
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31 ; GFX9-LABEL: s_cvt_pkrtz_v2f16_f32:
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32 ; GFX9: ; %bb.0:
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33 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
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35 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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173
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36 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
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37 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v2, s0, v0
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150
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38 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
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39 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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40 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
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41 ; GFX9-NEXT: s_endpgm
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42 %result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float %y)
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43 store <2 x half> %result, <2 x half> addrspace(1)* %out
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44 ret void
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45 }
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46
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47 define amdgpu_kernel void @s_cvt_pkrtz_samereg_v2f16_f32(<2 x half> addrspace(1)* %out, float %x) #0 {
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48 ; SI-LABEL: s_cvt_pkrtz_samereg_v2f16_f32:
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49 ; SI: ; %bb.0:
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50 ; SI-NEXT: s_load_dword s2, s[0:1], 0xb
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51 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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52 ; SI-NEXT: s_mov_b32 s7, 0xf000
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53 ; SI-NEXT: s_mov_b32 s6, -1
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54 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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55 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v0, s2, s2
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56 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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57 ; SI-NEXT: s_endpgm
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58 ;
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59 ; VI-LABEL: s_cvt_pkrtz_samereg_v2f16_f32:
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60 ; VI: ; %bb.0:
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61 ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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62 ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
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63 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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64 ; VI-NEXT: v_mov_b32_e32 v0, s2
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173
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65 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v2, s0, s0
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150
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66 ; VI-NEXT: v_mov_b32_e32 v1, s3
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67 ; VI-NEXT: flat_store_dword v[0:1], v2
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68 ; VI-NEXT: s_endpgm
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69 ;
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70 ; GFX9-LABEL: s_cvt_pkrtz_samereg_v2f16_f32:
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71 ; GFX9: ; %bb.0:
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72 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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73 ; GFX9-NEXT: s_load_dword s0, s[0:1], 0x2c
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74 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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75 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
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173
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76 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v2, s0, s0
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150
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77 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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78 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
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79 ; GFX9-NEXT: s_endpgm
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80 %result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float %x)
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81 store <2 x half> %result, <2 x half> addrspace(1)* %out
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82 ret void
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83 }
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84
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85 define amdgpu_kernel void @s_cvt_pkrtz_undef_undef(<2 x half> addrspace(1)* %out) #0 {
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86 ; GCN-LABEL: s_cvt_pkrtz_undef_undef:
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87 ; GCN: ; %bb.0:
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88 ; GCN-NEXT: s_endpgm
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89 %result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float undef)
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90 store <2 x half> %result, <2 x half> addrspace(1)* %out
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91 ret void
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92 }
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93
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94 define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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95 ; SI-LABEL: v_cvt_pkrtz_v2f16_f32:
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96 ; SI: ; %bb.0:
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97 ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
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98 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
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99 ; SI-NEXT: s_mov_b32 s3, 0xf000
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100 ; SI-NEXT: s_mov_b32 s2, 0
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101 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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102 ; SI-NEXT: v_mov_b32_e32 v1, 0
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103 ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
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104 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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105 ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
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106 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
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107 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64
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108 ; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
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109 ; SI-NEXT: s_waitcnt vmcnt(0)
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110 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v2, v2, v3
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111 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
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112 ; SI-NEXT: s_endpgm
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113 ;
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114 ; VI-LABEL: v_cvt_pkrtz_v2f16_f32:
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115 ; VI: ; %bb.0:
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116 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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117 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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118 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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119 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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120 ; VI-NEXT: v_mov_b32_e32 v1, s7
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121 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
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122 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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123 ; VI-NEXT: v_mov_b32_e32 v3, s1
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124 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
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125 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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173
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126 ; VI-NEXT: flat_load_dword v0, v[0:1]
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127 ; VI-NEXT: flat_load_dword v1, v[2:3]
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128 ; VI-NEXT: v_mov_b32_e32 v5, s5
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129 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
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130 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
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150
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131 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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173
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132 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1
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133 ; VI-NEXT: flat_store_dword v[4:5], v0
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150
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134 ; VI-NEXT: s_endpgm
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135 ;
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136 ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32:
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137 ; GFX9: ; %bb.0:
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138 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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139 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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140 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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141 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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142 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
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143 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
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144 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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145 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
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146 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
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147 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
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173
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148 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
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149 ; GFX9-NEXT: global_load_dword v1, v[2:3], off
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150 ; GFX9-NEXT: v_mov_b32_e32 v5, s5
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151 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4
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152 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
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150
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153 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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173
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154 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1
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155 ; GFX9-NEXT: global_store_dword v[4:5], v0, off
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150
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156 ; GFX9-NEXT: s_endpgm
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157 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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158 %tid.ext = sext i32 %tid to i64
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159 %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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160 %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
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161 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
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162 %a = load volatile float, float addrspace(1)* %a.gep
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163 %b = load volatile float, float addrspace(1)* %b.gep
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164 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %b)
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165 store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
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166 ret void
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167 }
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168
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169 define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_reg_imm(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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170 ; SI-LABEL: v_cvt_pkrtz_v2f16_f32_reg_imm:
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171 ; SI: ; %bb.0:
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172 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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173 ; SI-NEXT: s_mov_b32 s7, 0xf000
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174 ; SI-NEXT: s_mov_b32 s6, 0
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175 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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176 ; SI-NEXT: v_mov_b32_e32 v1, 0
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177 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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178 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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179 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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180 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
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181 ; SI-NEXT: s_waitcnt vmcnt(0)
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182 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, v2, 1.0
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183 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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184 ; SI-NEXT: s_endpgm
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185 ;
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186 ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_reg_imm:
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187 ; VI: ; %bb.0:
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188 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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189 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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190 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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191 ; VI-NEXT: v_mov_b32_e32 v1, s3
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192 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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193 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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173
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194 ; VI-NEXT: flat_load_dword v0, v[0:1]
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195 ; VI-NEXT: v_mov_b32_e32 v3, s1
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196 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
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197 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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150
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198 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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173
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199 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, 1.0
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200 ; VI-NEXT: flat_store_dword v[2:3], v0
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150
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201 ; VI-NEXT: s_endpgm
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202 ;
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203 ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_reg_imm:
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204 ; GFX9: ; %bb.0:
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205 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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206 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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207 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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208 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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209 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2
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210 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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173
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211 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
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212 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
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213 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
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214 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
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150
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215 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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173
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216 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, 1.0
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217 ; GFX9-NEXT: global_store_dword v[2:3], v0, off
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150
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218 ; GFX9-NEXT: s_endpgm
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219 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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220 %tid.ext = sext i32 %tid to i64
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221 %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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222 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
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223 %a = load volatile float, float addrspace(1)* %a.gep
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224 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float 1.0)
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225 store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
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226 ret void
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227 }
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228
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229 define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_imm_reg(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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230 ; SI-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg:
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231 ; SI: ; %bb.0:
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232 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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233 ; SI-NEXT: s_mov_b32 s7, 0xf000
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234 ; SI-NEXT: s_mov_b32 s6, 0
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235 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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236 ; SI-NEXT: v_mov_b32_e32 v1, 0
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237 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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238 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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239 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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240 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
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241 ; SI-NEXT: s_waitcnt vmcnt(0)
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242 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v2, 1.0, v2
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243 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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244 ; SI-NEXT: s_endpgm
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245 ;
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246 ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg:
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247 ; VI: ; %bb.0:
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248 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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|
|
249 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
|
250 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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|
|
251 ; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
|
252 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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|
|
253 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
173
|
254 ; VI-NEXT: flat_load_dword v0, v[0:1]
|
|
|
255 ; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
256 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
|
257 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
150
|
258 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
173
|
259 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, 1.0, v0
|
|
|
260 ; VI-NEXT: flat_store_dword v[2:3], v0
|
|
150
|
261 ; VI-NEXT: s_endpgm
|
|
|
262 ;
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|
|
263 ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg:
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|
|
264 ; GFX9: ; %bb.0:
|
|
|
265 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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|
|
266 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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|
|
267 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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|
|
268 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
|
|
|
269 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2
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|
|
270 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
173
|
271 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
|
|
|
272 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
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|
|
273 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
|
|
|
274 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
150
|
275 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
173
|
276 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, 1.0, v0
|
|
|
277 ; GFX9-NEXT: global_store_dword v[2:3], v0, off
|
|
150
|
278 ; GFX9-NEXT: s_endpgm
|
|
|
279 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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|
|
280 %tid.ext = sext i32 %tid to i64
|
|
|
281 %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
|
|
282 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
|
|
|
283 %a = load volatile float, float addrspace(1)* %a.gep
|
|
|
284 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 1.0, float %a)
|
|
|
285 store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
|
|
|
286 ret void
|
|
|
287 }
|
|
|
288
|
|
|
289 define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_fneg_lo(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
|
|
290 ; SI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo:
|
|
|
291 ; SI: ; %bb.0:
|
|
|
292 ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
|
|
293 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
|
|
294 ; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
295 ; SI-NEXT: s_mov_b32 s2, 0
|
|
|
296 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
|
297 ; SI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
298 ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
|
|
|
299 ; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
300 ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
|
|
|
301 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
|
|
|
302 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64
|
|
|
303 ; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
|
|
|
304 ; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
305 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -v2, v3
|
|
|
306 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
|
|
|
307 ; SI-NEXT: s_endpgm
|
|
|
308 ;
|
|
|
309 ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo:
|
|
|
310 ; VI: ; %bb.0:
|
|
|
311 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
312 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
313 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
314 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
315 ; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
316 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
317 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
318 ; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
319 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
320 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
173
|
321 ; VI-NEXT: flat_load_dword v0, v[0:1]
|
|
|
322 ; VI-NEXT: flat_load_dword v1, v[2:3]
|
|
|
323 ; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
324 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
325 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
150
|
326 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
173
|
327 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, v1
|
|
|
328 ; VI-NEXT: flat_store_dword v[4:5], v0
|
|
150
|
329 ; VI-NEXT: s_endpgm
|
|
|
330 ;
|
|
|
331 ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo:
|
|
|
332 ; GFX9: ; %bb.0:
|
|
|
333 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
334 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
335 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
336 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
337 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
|
|
338 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
|
|
339 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
340 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
|
|
341 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
|
|
342 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
173
|
343 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
|
|
|
344 ; GFX9-NEXT: global_load_dword v1, v[2:3], off
|
|
|
345 ; GFX9-NEXT: v_mov_b32_e32 v5, s5
|
|
|
346 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4
|
|
|
347 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
150
|
348 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
173
|
349 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, v1
|
|
|
350 ; GFX9-NEXT: global_store_dword v[4:5], v0, off
|
|
150
|
351 ; GFX9-NEXT: s_endpgm
|
|
|
352 %tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
353 %tid.ext = sext i32 %tid to i64
|
|
|
354 %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
|
|
355 %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
|
|
356 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
|
|
|
357 %a = load volatile float, float addrspace(1)* %a.gep
|
|
|
358 %b = load volatile float, float addrspace(1)* %b.gep
|
|
|
359 %neg.a = fsub float -0.0, %a
|
|
|
360 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %neg.a, float %b)
|
|
|
361 store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
|
|
|
362 ret void
|
|
|
363 }
|
|
|
364
|
|
|
365 define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_fneg_hi(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
|
|
366 ; SI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_hi:
|
|
|
367 ; SI: ; %bb.0:
|
|
|
368 ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
|
|
369 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
|
|
370 ; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
371 ; SI-NEXT: s_mov_b32 s2, 0
|
|
|
372 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
|
373 ; SI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
374 ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
|
|
|
375 ; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
376 ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
|
|
|
377 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
|
|
|
378 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64
|
|
|
379 ; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
|
|
|
380 ; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
381 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, v2, -v3
|
|
|
382 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
|
|
|
383 ; SI-NEXT: s_endpgm
|
|
|
384 ;
|
|
|
385 ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_hi:
|
|
|
386 ; VI: ; %bb.0:
|
|
|
387 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
388 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
389 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
390 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
391 ; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
392 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
393 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
394 ; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
395 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
396 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
173
|
397 ; VI-NEXT: flat_load_dword v0, v[0:1]
|
|
|
398 ; VI-NEXT: flat_load_dword v1, v[2:3]
|
|
|
399 ; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
400 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
401 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
150
|
402 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
173
|
403 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, -v1
|
|
|
404 ; VI-NEXT: flat_store_dword v[4:5], v0
|
|
150
|
405 ; VI-NEXT: s_endpgm
|
|
|
406 ;
|
|
|
407 ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_hi:
|
|
|
408 ; GFX9: ; %bb.0:
|
|
|
409 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
410 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
411 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
412 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
413 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
|
|
414 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
|
|
415 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
416 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
|
|
417 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
|
|
418 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
173
|
419 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
|
|
|
420 ; GFX9-NEXT: global_load_dword v1, v[2:3], off
|
|
|
421 ; GFX9-NEXT: v_mov_b32_e32 v5, s5
|
|
|
422 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4
|
|
|
423 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
150
|
424 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
173
|
425 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, -v1
|
|
|
426 ; GFX9-NEXT: global_store_dword v[4:5], v0, off
|
|
150
|
427 ; GFX9-NEXT: s_endpgm
|
|
|
428 %tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
429 %tid.ext = sext i32 %tid to i64
|
|
|
430 %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
|
|
431 %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
|
|
432 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
|
|
|
433 %a = load volatile float, float addrspace(1)* %a.gep
|
|
|
434 %b = load volatile float, float addrspace(1)* %b.gep
|
|
|
435 %neg.b = fsub float -0.0, %b
|
|
|
436 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %neg.b)
|
|
|
437 store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
|
|
|
438 ret void
|
|
|
439 }
|
|
|
440
|
|
|
441 define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_fneg_lo_hi(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
|
|
|
442 ; SI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo_hi:
|
|
|
443 ; SI: ; %bb.0:
|
|
|
444 ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
|
|
445 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
|
|
446 ; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
447 ; SI-NEXT: s_mov_b32 s2, 0
|
|
|
448 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
|
449 ; SI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
450 ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
|
|
|
451 ; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
452 ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
|
|
|
453 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
|
|
|
454 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64
|
|
|
455 ; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
|
|
|
456 ; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
457 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -v2, -v3
|
|
|
458 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
|
|
|
459 ; SI-NEXT: s_endpgm
|
|
|
460 ;
|
|
|
461 ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo_hi:
|
|
|
462 ; VI: ; %bb.0:
|
|
|
463 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
464 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
465 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
466 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
467 ; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
468 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
469 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
470 ; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
471 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
472 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
173
|
473 ; VI-NEXT: flat_load_dword v0, v[0:1]
|
|
|
474 ; VI-NEXT: flat_load_dword v1, v[2:3]
|
|
|
475 ; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
476 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
477 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
150
|
478 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
173
|
479 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, -v1
|
|
|
480 ; VI-NEXT: flat_store_dword v[4:5], v0
|
|
150
|
481 ; VI-NEXT: s_endpgm
|
|
|
482 ;
|
|
|
483 ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo_hi:
|
|
|
484 ; GFX9: ; %bb.0:
|
|
|
485 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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486 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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487 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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488 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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489 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
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490 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
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491 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
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492 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
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493 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
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494 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
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173
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495 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
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496 ; GFX9-NEXT: global_load_dword v1, v[2:3], off
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497 ; GFX9-NEXT: v_mov_b32_e32 v5, s5
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498 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4
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499 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
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150
|
500 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
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173
|
501 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, -v1
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502 ; GFX9-NEXT: global_store_dword v[4:5], v0, off
|
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150
|
503 ; GFX9-NEXT: s_endpgm
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|
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504 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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505 %tid.ext = sext i32 %tid to i64
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|
506 %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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507 %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
|
|
508 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
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509 %a = load volatile float, float addrspace(1)* %a.gep
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510 %b = load volatile float, float addrspace(1)* %b.gep
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|
|
511 %neg.a = fsub float -0.0, %a
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512 %neg.b = fsub float -0.0, %b
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|
513 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %neg.a, float %neg.b)
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514 store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
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515 ret void
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|
516 }
|
|
|
517
|
|
|
518 define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
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|
|
519 ; SI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi:
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|
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520 ; SI: ; %bb.0:
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|
|
521 ; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
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|
|
522 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
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|
|
523 ; SI-NEXT: s_mov_b32 s3, 0xf000
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|
|
524 ; SI-NEXT: s_mov_b32 s2, 0
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|
|
525 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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|
|
526 ; SI-NEXT: v_mov_b32_e32 v1, 0
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|
|
527 ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
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|
|
528 ; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
529 ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
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|
|
530 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
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|
|
531 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64
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|
|
532 ; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
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|
|
533 ; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
534 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -|v2|, -v3
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|
|
535 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
|
|
|
536 ; SI-NEXT: s_endpgm
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|
|
537 ;
|
|
|
538 ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi:
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|
|
539 ; VI: ; %bb.0:
|
|
|
540 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
541 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
542 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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|
|
543 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
544 ; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
|
545 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
|
|
|
546 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
547 ; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
548 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
|
|
|
549 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
173
|
550 ; VI-NEXT: flat_load_dword v0, v[0:1]
|
|
|
551 ; VI-NEXT: flat_load_dword v1, v[2:3]
|
|
|
552 ; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
|
553 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
|
|
|
554 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
150
|
555 ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
173
|
556 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -|v0|, -v1
|
|
|
557 ; VI-NEXT: flat_store_dword v[4:5], v0
|
|
150
|
558 ; VI-NEXT: s_endpgm
|
|
|
559 ;
|
|
|
560 ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi:
|
|
|
561 ; GFX9: ; %bb.0:
|
|
|
562 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
|
563 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
|
564 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v0
|
|
|
565 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
566 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
|
|
|
567 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s6, v4
|
|
|
568 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
569 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
|
|
|
570 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
|
|
|
571 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
173
|
572 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
|
|
|
573 ; GFX9-NEXT: global_load_dword v1, v[2:3], off
|
|
|
574 ; GFX9-NEXT: v_mov_b32_e32 v5, s5
|
|
|
575 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s4, v4
|
|
|
576 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
150
|
577 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
173
|
578 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v0, -|v0|, -v1
|
|
|
579 ; GFX9-NEXT: global_store_dword v[4:5], v0, off
|
|
150
|
580 ; GFX9-NEXT: s_endpgm
|
|
|
581 %tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
582 %tid.ext = sext i32 %tid to i64
|
|
|
583 %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
|
|
|
584 %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
|
|
|
585 %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
|
|
|
586 %a = load volatile float, float addrspace(1)* %a.gep
|
|
|
587 %b = load volatile float, float addrspace(1)* %b.gep
|
|
|
588 %fabs.a = call float @llvm.fabs.f32(float %a)
|
|
|
589 %neg.fabs.a = fsub float -0.0, %fabs.a
|
|
|
590 %neg.b = fsub float -0.0, %b
|
|
|
591 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %neg.fabs.a, float %neg.b)
|
|
|
592 store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
|
|
|
593 ret void
|
|
|
594 }
|
|
|
595
|
|
|
596 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
|
|
|
597 declare float @llvm.fabs.f32(float) #1
|
|
|
598 declare i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
599
|
|
|
600
|
|
|
601 attributes #0 = { nounwind }
|
|
|
602 attributes #1 = { nounwind readnone }
|
