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150
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1 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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2 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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3 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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4 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
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5 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
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6
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7 ; Minimum offset
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8 ; GCN-LABEL: {{^}}gws_init_offset0:
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9 ; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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10 ; GCN-DAG: s_mov_b32 m0, 0{{$}}
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11 ; GCN: v_mov_b32_e32 v0, [[BAR_NUM]]
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12 ; NOLOOP: ds_gws_init v0 gds{{$}}
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13
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14 ; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]:
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15 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
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16 ; LOOP-NEXT: ds_gws_init v0 gds
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17 ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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18 ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
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19 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
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20 ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
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21 define amdgpu_kernel void @gws_init_offset0(i32 %val) #0 {
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22 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
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23 ret void
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24 }
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25
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26 ; Maximum offset
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27 ; GCN-LABEL: {{^}}gws_init_offset63:
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28 ; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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29 ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
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30 ; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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31 ; NOLOOP: ds_gws_init v0 offset:63 gds{{$}}
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32
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33
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34 ; LOOP: s_mov_b32 m0, 0{{$}}
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35 ; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]:
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36 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
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37 ; LOOP-NEXT: ds_gws_init v0 offset:63 gds
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38 ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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39 ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
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40 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
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41 ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
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42 define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 {
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43 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63)
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44 ret void
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45 }
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46
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47 ; FIXME: Should be able to shift directly into m0
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48 ; GCN-LABEL: {{^}}gws_init_sgpr_offset:
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49 ; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
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50
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51 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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52 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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53
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54 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
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55
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56 ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
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57 ; NOLOOP: ds_gws_init [[GWS_VAL]] gds{{$}}
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58 define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 {
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59 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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60 ret void
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61 }
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62
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63 ; Variable offset in SGPR with constant add
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64 ; GCN-LABEL: {{^}}gws_init_sgpr_offset_add1:
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65 ; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
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66
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67 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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68 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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69
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70 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
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71
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72 ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
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73 ; NOLOOP: ds_gws_init [[GWS_VAL]] offset:1 gds{{$}}
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74 define amdgpu_kernel void @gws_init_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {
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75 %offset = add i32 %offset.base, 1
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76 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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77 ret void
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78 }
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79
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80 ; GCN-LABEL: {{^}}gws_init_vgpr_offset:
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81 ; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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82 ; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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83
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84 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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85 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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86
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87 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
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88
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89 ; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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90 ; NOLOOP: ds_gws_init v0 gds{{$}}
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91 define amdgpu_kernel void @gws_init_vgpr_offset(i32 %val) #0 {
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92 %vgpr.offset = call i32 @llvm.amdgcn.workitem.id.x()
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93 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)
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94 ret void
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95 }
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96
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97 ; Variable offset in VGPR with constant add
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98 ; GCN-LABEL: {{^}}gws_init_vgpr_offset_add:
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99 ; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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100 ; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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101
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102 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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103 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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104
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105 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
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106
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107 ; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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108 ; NOLOOP: ds_gws_init v0 offset:3 gds{{$}}
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109 define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
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110 %vgpr.offset.base = call i32 @llvm.amdgcn.workitem.id.x()
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111 %vgpr.offset = add i32 %vgpr.offset.base, 3
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112 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)
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113 ret void
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114 }
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115
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116 @lds = internal unnamed_addr addrspace(3) global i32 undef
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117
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118 ; Check if m0 initialization is shared.
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119 ; GCN-LABEL: {{^}}gws_init_save_m0_init_constant_offset:
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120 ; NOLOOP: s_mov_b32 m0, 0
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121 ; NOLOOP: ds_gws_init v{{[0-9]+}} offset:10 gds
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122
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123 ; LOOP: s_mov_b32 m0, -1
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124 ; LOOP: ds_write_b32
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125 ; LOOP: s_mov_b32 m0, 0
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126 ; LOOP: s_setreg_imm32_b32
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127 ; LOOP: ds_gws_init v{{[0-9]+}} offset:10 gds
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128 ; LOOP: s_cbranch_scc1
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129
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130 ; LOOP: s_mov_b32 m0, -1
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131 ; LOOP: ds_write_b32
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132 define amdgpu_kernel void @gws_init_save_m0_init_constant_offset(i32 %val) #0 {
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133 store volatile i32 1, i32 addrspace(3)* @lds
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134 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 10)
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135 store i32 2, i32 addrspace(3)* @lds
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136 ret void
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137 }
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138
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139 ; GCN-LABEL: {{^}}gws_init_lgkmcnt:
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140 ; NOLOOP: s_mov_b32 m0, 0{{$}}
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141 ; NOLOOP: ds_gws_init v0 gds{{$}}
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142 ; NOLOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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143 ; NOLOOP-NEXT: s_setpc_b64
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144 define void @gws_init_lgkmcnt(i32 %val) {
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145 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
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146 ret void
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147 }
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148
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149 ; Does not imply memory fence on its own
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150 ; GCN-LABEL: {{^}}gws_init_wait_before:
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151 ; NOLOOP: s_waitcnt lgkmcnt(0)
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152 ; NOLOOP-NOT: s_waitcnt
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153 ; NOLOOP: ds_gws_init
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154 ; NOLOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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155 define amdgpu_kernel void @gws_init_wait_before(i32 %val, i32 addrspace(1)* %ptr) #0 {
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156 store i32 0, i32 addrspace(1)* %ptr
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157 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)
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158 ret void
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159 }
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160
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161 declare void @llvm.amdgcn.ds.gws.init(i32, i32) #1
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162 declare i32 @llvm.amdgcn.workitem.id.x() #2
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163
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164 attributes #0 = { nounwind }
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165 attributes #1 = { convergent inaccessiblememonly nounwind writeonly }
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166 attributes #2 = { nounwind readnone speculatable }
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