annotate llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll @ 206:f17a3b42b08b

Added tag before-12 for changeset b7591485f4cd
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 07 Jun 2021 21:25:57 +0900
parents 1d019706d866
children c4bab56944e8
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1 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032 %s
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2
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3 ; GCN-LABEL: {{^}}test_init_exec:
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4 ; GFX1032: s_mov_b32 exec_lo, 0x12345
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5 ; GFX1064: s_mov_b64 exec, 0x12345
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6 ; GCN: v_add_f32_e32 v0,
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7 define amdgpu_ps float @test_init_exec(float %a, float %b) {
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8 main_body:
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9 %s = fadd float %a, %b
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10 call void @llvm.amdgcn.init.exec(i64 74565)
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11 ret float %s
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12 }
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13
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14 ; GCN-LABEL: {{^}}test_init_exec_from_input:
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15 ; GCN: s_bfe_u32 s0, s3, 0x70008
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16 ; GFX1032: s_bfm_b32 exec_lo, s0, 0
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17 ; GFX1032: s_cmp_eq_u32 s0, 32
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18 ; GFX1032: s_cmov_b32 exec_lo, -1
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19 ; GFX1064: s_bfm_b64 exec, s0, 0
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20 ; GFX1064: s_cmp_eq_u32 s0, 64
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21 ; GFX1064: s_cmov_b64 exec, -1
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22 ; GCN: v_add_f32_e32 v0,
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23 define amdgpu_ps float @test_init_exec_from_input(i32 inreg, i32 inreg, i32 inreg, i32 inreg %count, float %a, float %b) {
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24 main_body:
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25 %s = fadd float %a, %b
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26 call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8)
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27 ret float %s
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28 }
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29
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30 declare void @llvm.amdgcn.init.exec(i64)
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31 declare void @llvm.amdgcn.init.exec.from.input(i32, i32)