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150
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1 ;RUN: llc < %s -march=amdgcn -mcpu=gfx700 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN
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2
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3 ; GCN-LABEL: {{^}}tbuffer_raw_store_immoffs_x3:
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4 ; GCN: tbuffer_store_format_xyz v[0:2], off, s[0:3], dfmt:5, nfmt:7, 0 offset:42
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5 define amdgpu_ps void @tbuffer_raw_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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6 main_body:
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7 %in1 = bitcast <3 x float> %1 to <3 x i32>
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8 call void @llvm.amdgcn.raw.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 42, i32 0, i32 117, i32 0)
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9 ret void
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10 }
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11
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12
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13 ; GCN-LABEL: {{^}}tbuffer_struct_store_immoffs_x3:
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14 ; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
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15 ; GCN: tbuffer_store_format_xyz v[0:2], [[ZEROREG]], s[0:3], dfmt:5, nfmt:7, 0 idxen offset:42
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16 define amdgpu_ps void @tbuffer_struct_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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17 main_body:
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18 %in1 = bitcast <3 x float> %1 to <3 x i32>
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19 call void @llvm.amdgcn.struct.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 117, i32 0)
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20 ret void
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21 }
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22
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23 ; GCN-LABEL: {{^}}tbuffer_store_immoffs_x3:
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24 ; GCN: tbuffer_store_format_xyz v[0:2], off, s[0:3], dfmt:5, nfmt:7, 0 offset:42
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25 define amdgpu_ps void @tbuffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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26 main_body:
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27 %in1 = bitcast <3 x float> %1 to <3 x i32>
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28 call void @llvm.amdgcn.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 42, i32 5, i32 7, i1 0, i1 0)
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29 ret void
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30 }
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31
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32 declare void @llvm.amdgcn.raw.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32) #0
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33 declare void @llvm.amdgcn.struct.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32, i32) #0
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34 declare void @llvm.amdgcn.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #0
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35
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