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annotate llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll @ 206:f17a3b42b08b

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Added tag before-12 for changeset b7591485f4cd
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 07 Jun 2021 21:25:57 +0900
parents 1d019706d866
children 2e18cbf3894f
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1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CI,CIGFX9 %s
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2 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,GFX9,CIGFX9 %s
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3 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
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4
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5 declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #0
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6
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7 ; CHECK-LABEL: {{^}}test_writelane_sreg:
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8 ; CIGFX9: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, m0
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9 ; GFX10: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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10 define amdgpu_kernel void @test_writelane_sreg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
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11 %oldval = load i32, i32 addrspace(1)* %out
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12 %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
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13 store i32 %writelane, i32 addrspace(1)* %out, align 4
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14 ret void
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15 }
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16
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17 ; CHECK-LABEL: {{^}}test_writelane_imm_sreg:
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18 ; CHECK: v_writelane_b32 v{{[0-9]+}}, 32, s{{[0-9]+}}
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19 define amdgpu_kernel void @test_writelane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
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20 %oldval = load i32, i32 addrspace(1)* %out
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21 %writelane = call i32 @llvm.amdgcn.writelane(i32 32, i32 %src1, i32 %oldval)
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22 store i32 %writelane, i32 addrspace(1)* %out, align 4
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23 ret void
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24 }
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25
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26 ; CHECK-LABEL: {{^}}test_writelane_vreg_lane:
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27 ; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
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28 ; CHECK: v_writelane_b32 v{{[0-9]+}}, 12, [[LANE]]
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29 define amdgpu_kernel void @test_writelane_vreg_lane(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
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30 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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31 %gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid
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32 %args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
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33 %oldval = load i32, i32 addrspace(1)* %out
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34 %lane = extractelement <2 x i32> %args, i32 1
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35 %writelane = call i32 @llvm.amdgcn.writelane(i32 12, i32 %lane, i32 %oldval)
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36 store i32 %writelane, i32 addrspace(1)* %out, align 4
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37 ret void
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38 }
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39
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40 ; CHECK-LABEL: {{^}}test_writelane_m0_sreg:
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41 ; CHECK: s_mov_b32 m0, -1
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42 ; CIGFX9: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
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43 ; CIGFX9: v_writelane_b32 v{{[0-9]+}}, [[COPY_M0]], m0
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44 ; GFX10: v_writelane_b32 v{{[0-9]+}}, m0, s{{[0-9]+}}
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45 define amdgpu_kernel void @test_writelane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
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46 %oldval = load i32, i32 addrspace(1)* %out
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47 %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
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48 %writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %src1, i32 %oldval)
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49 store i32 %writelane, i32 addrspace(1)* %out, align 4
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50 ret void
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51 }
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52
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53 ; CHECK-LABEL: {{^}}test_writelane_imm:
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54 ; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 32
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55 define amdgpu_kernel void @test_writelane_imm(i32 addrspace(1)* %out, i32 %src0) #1 {
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56 %oldval = load i32, i32 addrspace(1)* %out
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57 %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 32, i32 %oldval) #0
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58 store i32 %writelane, i32 addrspace(1)* %out, align 4
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59 ret void
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60 }
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61
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62 ; CHECK-LABEL: {{^}}test_writelane_sreg_oldval:
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63 ; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], s{{[0-9]+}}
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64 ; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
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65 ; GFX10: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
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66 define amdgpu_kernel void @test_writelane_sreg_oldval(i32 inreg %oldval, i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
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67 %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
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68 store i32 %writelane, i32 addrspace(1)* %out, align 4
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69 ret void
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70 }
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71
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72 ; CHECK-LABEL: {{^}}test_writelane_imm_oldval:
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73 ; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], 42
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74 ; CIGFX9: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, m0
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75 ; GFX10: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
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76 define amdgpu_kernel void @test_writelane_imm_oldval(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
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77 %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 42)
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78 store i32 %writelane, i32 addrspace(1)* %out, align 4
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79 ret void
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80 }
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81
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82 declare i32 @llvm.amdgcn.workitem.id.x() #2
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83
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84 attributes #0 = { nounwind readnone convergent }
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85 attributes #1 = { nounwind }
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86 attributes #2 = { nounwind readnone }