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annotate llvm/test/CodeGen/AMDGPU/llvm.log.f16.ll @ 206:f17a3b42b08b

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Added tag before-12 for changeset b7591485f4cd
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 07 Jun 2021 21:25:57 +0900
parents 1d019706d866
children 2e18cbf3894f
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=FUNC %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=VIGFX9 -check-prefix=FUNC %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=VIGFX9 -check-prefix=FUNC %s
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4
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5 declare half @llvm.log.f16(half %a)
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6 declare <2 x half> @llvm.log.v2f16(<2 x half> %a)
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7
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8 ; FUNC-LABEL: {{^}}log_f16
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9 ; SI: buffer_load_ushort v[[A_F16_0:[0-9]+]]
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10 ; VI: flat_load_ushort v[[A_F16_0:[0-9]+]]
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11 ; GFX9: global_load_ushort v[[A_F16_0:[0-9]+]]
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12 ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
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13 ; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
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14 ; SI: v_mul_f32_e32 v[[R_F32_1:[0-9]+]], 0x3f317218, v[[R_F32_0]]
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15 ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_1]]
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16 ; VIGFX9: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
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17 ; VIGFX9: v_mul_f16_e32 v[[R_F16_0]], 0x398c, v[[R_F16_0]]
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18 ; SI: buffer_store_short v[[R_F16_0]], v{{\[[0-9]+:[0-9]+\]}}
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19 ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
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20 ; GFX9: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[R_F16_0]]
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21 define void @log_f16(
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22 half addrspace(1)* %r,
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23 half addrspace(1)* %a) {
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24 entry:
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25 %a.val = load half, half addrspace(1)* %a
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26 %r.val = call half @llvm.log.f16(half %a.val)
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27 store half %r.val, half addrspace(1)* %r
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28 ret void
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29 }
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30
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31 ; FUNC-LABEL: {{^}}log_v2f16
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32 ; SI: buffer_load_dword v[[A_F16_0:[0-9]+]]
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33 ; VI: flat_load_dword v[[A_F16_0:[0-9]+]]
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34 ; GFX9: global_load_dword v[[A_F16_0:[0-9]+]]
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35 ; SI: s_mov_b32 [[A_F32_2:s[0-9]+]], 0x3f317218
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36 ; VIGFX9: s_movk_i32 [[A_F32_2:s[0-9]+]], 0x398c
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37 ; VI: v_mov_b32_e32 [[A_F32_2_V:v[0-9]+]], [[A_F32_2]]
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38 ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
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39 ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_1]]
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40 ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_0]]
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41 ; SI: v_log_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
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42 ; SI: v_log_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
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43 ; SI: v_mul_f32_e32 v[[R_F32_5:[0-9]+]], [[A_F32_2]], v[[R_F32_0]]
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44 ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_5]]
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45 ; SI: v_mul_f32_e32 v[[R_F32_6:[0-9]+]], [[A_F32_2]], v[[R_F32_1]]
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46 ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_6]]
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47 ; GFX9: v_log_f16_e32 v[[R_F16_2:[0-9]+]], v[[A_F16_0]]
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48 ; VIGFX9: v_log_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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49 ; VI: v_log_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_F16_0]]
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50 ; VI: v_mul_f16_sdwa v[[R_F16_2:[0-9]+]], v[[R_F16_1]], [[A_F32_2_V]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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51 ; GFX9: v_mul_f16_e32 v[[R_F32_3:[0-9]+]], [[A_F32_2]], v[[R_F16_2]]
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52 ; VIGFX9: v_mul_f16_e32 v[[R_F32_2:[0-9]+]], [[A_F32_2]], v[[R_F16_0]]
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53 ; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_0]]
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54 ; SI-NOT: v_and_b32_e32
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55 ; SI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_1]], v[[R_F16_0]]
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56 ; VI-NOT: v_and_b32_e32
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57 ; VI: v_or_b32_e32 v[[R_F32_5:[0-9]+]], v[[R_F16_0]], v[[R_F16_2]]
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58 ; GFX9: v_and_b32_e32 v[[R_F32_4:[0-9]+]], 0xffff, v[[R_F32_3]]
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59 ; GFX9: v_lshl_or_b32 v[[R_F32_5:[0-9]+]], v[[R_F32_2]], 16, v[[R_F32_4]]
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60 ; SI: buffer_store_dword v[[R_F32_5]]
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61 ; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
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62 ; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[R_F32_5]]
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63 define void @log_v2f16(
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64 <2 x half> addrspace(1)* %r,
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65 <2 x half> addrspace(1)* %a) {
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66 entry:
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67 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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68 %r.val = call <2 x half> @llvm.log.v2f16(<2 x half> %a.val)
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69 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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70 ret void
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71 }