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annotate llvm/test/CodeGen/AMDGPU/llvm.log2.ll @ 206:f17a3b42b08b

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Added tag before-12 for changeset b7591485f4cd
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 07 Jun 2021 21:25:57 +0900
parents 1d019706d866
children 1f2b6ac9f198
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1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=EG --check-prefix=FUNC
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2 ;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CM --check-prefix=FUNC
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3 ;RUN: llc < %s -march=amdgcn -mcpu=tahiti | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=SI --check-prefix=FUNC
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4 ;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=SI --check-prefix=FUNC
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5
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6 ;FUNC-LABEL: {{^}}test:
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7 ;EG: LOG_IEEE
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8 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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9 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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10 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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11 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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12 ;SI: v_log_f32
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13
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14 define amdgpu_kernel void @test(float addrspace(1)* %out, float %in) {
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15 entry:
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16 %0 = call float @llvm.log2.f32(float %in)
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17 store float %0, float addrspace(1)* %out
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18 ret void
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19 }
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20
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21 ;FUNC-LABEL: {{^}}testv2:
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22 ;EG: LOG_IEEE
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23 ;EG: LOG_IEEE
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24 ; FIXME: We should be able to merge these packets together on Cayman so we
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25 ; have a maximum of 4 instructions.
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26 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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27 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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28 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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29 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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30 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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31 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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32 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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33 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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34 ;SI: v_log_f32
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35 ;SI: v_log_f32
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36
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37 define amdgpu_kernel void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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38 entry:
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39 %0 = call <2 x float> @llvm.log2.v2f32(<2 x float> %in)
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40 store <2 x float> %0, <2 x float> addrspace(1)* %out
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41 ret void
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42 }
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43
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44 ;FUNC-LABEL: {{^}}testv4:
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45 ;EG: LOG_IEEE
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46 ;EG: LOG_IEEE
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47 ;EG: LOG_IEEE
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48 ;EG: LOG_IEEE
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49 ; FIXME: We should be able to merge these packets together on Cayman so we
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50 ; have a maximum of 4 instructions.
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51 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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52 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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53 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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54 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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55 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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56 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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57 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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58 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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59 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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60 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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61 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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62 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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63 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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64 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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65 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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66 ;CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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67 ;SI: v_log_f32
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68 ;SI: v_log_f32
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69 ;SI: v_log_f32
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70 ;SI: v_log_f32
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71 define amdgpu_kernel void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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72 entry:
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73 %0 = call <4 x float> @llvm.log2.v4f32(<4 x float> %in)
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74 store <4 x float> %0, <4 x float> addrspace(1)* %out
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75 ret void
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76 }
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77
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78 declare float @llvm.log2.f32(float) readnone
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79 declare <2 x float> @llvm.log2.v2f32(<2 x float>) readnone
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80 declare <4 x float> @llvm.log2.v4f32(<4 x float>) readnone