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150
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1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX678,HAS-ATOMICS %s
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2 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,HAS-ATOMICS %s
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3 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX678,NO-ATOMICS %s
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4 ; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX678,NO-ATOMICS %s
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5
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6 ; GCN-LABEL: {{^}}lds_atomic_fadd_ret_f32:
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7 ; GFX678-DAG: s_mov_b32 m0
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8 ; GFX9-NOT: m0
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9 ; HAS-ATOMICS-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 4.0
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10 ; HAS-ATOMICS: ds_add_rtn_f32 v0, v0, [[K]]
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11
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12 ; NO-ATOMICS: ds_read_b32
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13 ; NO-ATOMICS: v_add_f32
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14 ; NO-ATOMICS: ds_cmpst_rtn_b32
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15 ; NO-ATOMICS: s_cbranch_execnz
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16 define float @lds_atomic_fadd_ret_f32(float addrspace(3)* %ptr) nounwind {
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17 %result = atomicrmw fadd float addrspace(3)* %ptr, float 4.0 seq_cst
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18 ret float %result
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19 }
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20
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21 ; GCN-LABEL: {{^}}lds_atomic_fadd_noret_f32:
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22 ; GFX678-DAG: s_mov_b32 m0
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23 ; GFX9-NOT: m0
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24 ; HAS-ATOMICS-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 4.0
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25 ; HAS-ATOMICS: ds_add_f32 v0, [[K]]
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26 define void @lds_atomic_fadd_noret_f32(float addrspace(3)* %ptr) nounwind {
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27 %result = atomicrmw fadd float addrspace(3)* %ptr, float 4.0 seq_cst
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28 ret void
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29 }
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30
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31 ; GCN-LABEL: {{^}}lds_ds_fadd:
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32 ; VI-DAG: s_mov_b32 m0
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33 ; GFX9-NOT: m0
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34 ; HAS-ATOMICS-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
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35 ; HAS-ATOMICS: ds_add_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32
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36 ; HAS-ATOMICS: ds_add_f32 [[V3:v[0-9]+]], [[V0]] offset:64
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37 ; HAS-ATOMICS: s_waitcnt vmcnt(0) lgkmcnt(0)
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38 ; HAS-ATOMICS: ds_add_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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39 define amdgpu_kernel void @lds_ds_fadd(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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40 %idx.add = add nuw i32 %idx, 4
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41 %shl0 = shl i32 %idx.add, 3
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42 %shl1 = shl i32 %idx.add, 4
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43 %ptr0 = inttoptr i32 %shl0 to float addrspace(3)*
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44 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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45 %a1 = atomicrmw fadd float addrspace(3)* %ptr0, float 4.2e+1 seq_cst
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46 %a2 = atomicrmw fadd float addrspace(3)* %ptr1, float 4.2e+1 seq_cst
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47 %a3 = atomicrmw fadd float addrspace(3)* %ptrf, float %a1 seq_cst
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48 store float %a3, float addrspace(1)* %out
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49 ret void
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50 }
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51
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52 ; GCN-LABEL: {{^}}lds_ds_fadd_one_as:
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53 ; VI-DAG: s_mov_b32 m0
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54 ; GFX9-NOT: m0
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55 ; HAS-ATOMICS-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
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56 ; HAS-ATOMICS: ds_add_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32
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57 ; HAS-ATOMICS: ds_add_f32 [[V3:v[0-9]+]], [[V0]] offset:64
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58 ; HAS-ATOMICS: s_waitcnt lgkmcnt(1)
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59 ; HAS-ATOMICS: ds_add_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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60 define amdgpu_kernel void @lds_ds_fadd_one_as(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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61 %idx.add = add nuw i32 %idx, 4
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62 %shl0 = shl i32 %idx.add, 3
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63 %shl1 = shl i32 %idx.add, 4
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64 %ptr0 = inttoptr i32 %shl0 to float addrspace(3)*
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65 %ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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66 %a1 = atomicrmw fadd float addrspace(3)* %ptr0, float 4.2e+1 syncscope("one-as") seq_cst
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67 %a2 = atomicrmw fadd float addrspace(3)* %ptr1, float 4.2e+1 syncscope("one-as") seq_cst
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68 %a3 = atomicrmw fadd float addrspace(3)* %ptrf, float %a1 syncscope("one-as") seq_cst
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69 store float %a3, float addrspace(1)* %out
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70 ret void
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71 }
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72
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73 ; GCN-LABEL: {{^}}lds_atomic_fadd_ret_f64:
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74 ; GCN: ds_read_b64
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75 ; GCN: v_add_f64
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76 ; GCN: ds_cmpst_rtn_b64
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77 ; GCN: s_cbranch_execnz
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78 define double @lds_atomic_fadd_ret_f64(double addrspace(3)* %ptr) nounwind {
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79 %result = atomicrmw fadd double addrspace(3)* %ptr, double 4.0 seq_cst
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80 ret double %result
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81 }
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82
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83 ; GCN-LABEL: {{^}}lds_atomic_fadd_noret_f64:
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84 ; GCN: ds_read_b64
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85 ; GCN: v_add_f64
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86 ; GCN: ds_cmpst_rtn_b64
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87 ; GCN: s_cbranch_execnz
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88 define void @lds_atomic_fadd_noret_f64(double addrspace(3)* %ptr) nounwind {
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89 %result = atomicrmw fadd double addrspace(3)* %ptr, double 4.0 seq_cst
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90 ret void
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91 }
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92
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93 ; GCN-LABEL: {{^}}lds_atomic_fsub_ret_f32:
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94 ; GCN: ds_read_b32
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95 ; GCN: v_sub_f32
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96 ; GCN: ds_cmpst_rtn_b32
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97 ; GCN: s_cbranch_execnz
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98 define float @lds_atomic_fsub_ret_f32(float addrspace(3)* %ptr, float %val) nounwind {
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99 %result = atomicrmw fsub float addrspace(3)* %ptr, float %val seq_cst
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100 ret float %result
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101 }
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102
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103 ; GCN-LABEL: {{^}}lds_atomic_fsub_noret_f32:
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104 ; GCN: ds_read_b32
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105 ; GCN: v_sub_f32
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106 ; GCN: ds_cmpst_rtn_b32
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107 define void @lds_atomic_fsub_noret_f32(float addrspace(3)* %ptr, float %val) nounwind {
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108 %result = atomicrmw fsub float addrspace(3)* %ptr, float %val seq_cst
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109 ret void
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110 }
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111
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112 ; GCN-LABEL: {{^}}lds_atomic_fsub_ret_f64:
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113 ; GCN: ds_read_b64
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114 ; GCN: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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115 ; GCN: ds_cmpst_rtn_b64
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116
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117 define double @lds_atomic_fsub_ret_f64(double addrspace(3)* %ptr, double %val) nounwind {
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118 %result = atomicrmw fsub double addrspace(3)* %ptr, double %val seq_cst
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119 ret double %result
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120 }
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121
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122 ; GCN-LABEL: {{^}}lds_atomic_fsub_noret_f64:
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123 ; GCN: ds_read_b64
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124 ; GCN: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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125 ; GCN: ds_cmpst_rtn_b64
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126 ; GCN: s_cbranch_execnz
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127 define void @lds_atomic_fsub_noret_f64(double addrspace(3)* %ptr, double %val) nounwind {
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128 %result = atomicrmw fsub double addrspace(3)* %ptr, double %val seq_cst
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129 ret void
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130 }
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