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150
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs -o /dev/null < %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o /dev/null < %s
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3
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4 ; The register coalescer introduces a verifier error which later
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5 ; results in a crash during scheduling.
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6
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7 declare i32 @llvm.amdgcn.workitem.id.x() #0
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8
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9 define amdgpu_kernel void @reg_coalescer_breaks_dead(<2 x i32> addrspace(1)* nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3) #1 {
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10 bb:
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11 %id.x = call i32 @llvm.amdgcn.workitem.id.x()
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12 %cmp0 = icmp eq i32 %id.x, 0
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13 br i1 %cmp0, label %bb3, label %bb4
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14
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15 bb3: ; preds = %bb
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16 %tmp = ashr exact i32 undef, 8
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17 br label %bb6
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18
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19 bb4: ; preds = %bb6, %bb
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20 %tmp5 = phi <2 x i32> [ zeroinitializer, %bb ], [ %tmp13, %bb6 ]
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21 br i1 undef, label %bb15, label %bb16
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22
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23 bb6: ; preds = %bb6, %bb3
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24 %tmp7 = phi <2 x i32> [ zeroinitializer, %bb3 ], [ %tmp13, %bb6 ]
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25 %tmp8 = add nsw i32 0, %arg1
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26 %tmp9 = add nsw i32 %tmp8, 0
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27 %tmp10 = sext i32 %tmp9 to i64
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28 %tmp11 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %arg, i64 %tmp10
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29 %tmp12 = load <2 x i32>, <2 x i32> addrspace(1)* %tmp11, align 8
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30 %tmp13 = add <2 x i32> %tmp12, %tmp7
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31 %tmp14 = icmp slt i32 undef, %arg2
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32 br i1 %tmp14, label %bb6, label %bb4
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33
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34 bb15: ; preds = %bb4
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35 store <2 x i32> %tmp5, <2 x i32> addrspace(3)* undef, align 8
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36 br label %bb16
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37
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38 bb16: ; preds = %bb15, %bb4
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39 unreachable
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40 }
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41
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42 attributes #0 = { nounwind readnone }
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43 attributes #1 = { nounwind }
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