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150
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2
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3 ; Make sure to test with f32 and i32 compares. If we have to use float
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4 ; compares, we always have multiple condition registers. If we can do
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5 ; scalar compares, we don't want to use multiple condition registers.
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6
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7 ; GCN-LABEL: {{^}}opt_select_i32_and_cmp_i32:
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8 ; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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9 ; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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10 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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11 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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12 ; GCN-NOT: [[RESULT]]
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13 ; GCN: buffer_store_dword [[RESULT]]
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14 define amdgpu_kernel void @opt_select_i32_and_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 {
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15 %icmp0 = icmp ne i32 %a, %b
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16 %icmp1 = icmp ne i32 %a, %c
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17 %and = and i1 %icmp0, %icmp1
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18 %select = select i1 %and, i32 %x, i32 %y
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19 store i32 %select, i32 addrspace(1)* %out
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20 ret void
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21 }
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22
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23 ; GCN-LABEL: {{^}}opt_select_i32_and_cmp_f32:
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24 ; GCN-DAG: v_cmp_lg_f32_e32 vcc
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25 ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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26 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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27 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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28 ; GCN-NOT: [[RESULT]]
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29 ; GCN: buffer_store_dword [[RESULT]]
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30 define amdgpu_kernel void @opt_select_i32_and_cmp_f32(i32 addrspace(1)* %out, float %a, float %b, float %c, i32 %x, i32 %y) #0 {
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31 %fcmp0 = fcmp one float %a, %b
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32 %fcmp1 = fcmp one float %a, %c
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33 %and = and i1 %fcmp0, %fcmp1
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34 %select = select i1 %and, i32 %x, i32 %y
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35 store i32 %select, i32 addrspace(1)* %out
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36 ret void
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37 }
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38
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39 ; GCN-LABEL: {{^}}opt_select_i64_and_cmp_i32:
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40 ; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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41 ; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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42 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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43 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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44 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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45 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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46 define amdgpu_kernel void @opt_select_i64_and_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
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47 %icmp0 = icmp ne i32 %a, %b
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48 %icmp1 = icmp ne i32 %a, %c
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49 %and = and i1 %icmp0, %icmp1
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50 %select = select i1 %and, i64 %x, i64 %y
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51 store i64 %select, i64 addrspace(1)* %out
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52 ret void
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53 }
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54
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55 ; GCN-LABEL: {{^}}opt_select_i64_and_cmp_f32:
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56 ; GCN-DAG: v_cmp_lg_f32_e32 vcc,
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57 ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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58 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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59 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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60 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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61 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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62 define amdgpu_kernel void @opt_select_i64_and_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 {
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63 %fcmp0 = fcmp one float %a, %b
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64 %fcmp1 = fcmp one float %a, %c
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65 %and = and i1 %fcmp0, %fcmp1
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66 %select = select i1 %and, i64 %x, i64 %y
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67 store i64 %select, i64 addrspace(1)* %out
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68 ret void
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69 }
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70
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71 ; GCN-LABEL: {{^}}opt_select_i32_or_cmp_i32:
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72 ; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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73 ; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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74 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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75 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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76 ; GCN-NOT: [[RESULT]]
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77 ; GCN: buffer_store_dword [[RESULT]]
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78 ; GCN: s_endpgm
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79 define amdgpu_kernel void @opt_select_i32_or_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 {
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80 %icmp0 = icmp ne i32 %a, %b
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81 %icmp1 = icmp ne i32 %a, %c
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82 %or = or i1 %icmp0, %icmp1
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83 %select = select i1 %or, i32 %x, i32 %y
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84 store i32 %select, i32 addrspace(1)* %out
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85 ret void
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86 }
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87
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88 ; GCN-LABEL: {{^}}opt_select_i32_or_cmp_f32:
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89 ; GCN-DAG: v_cmp_lg_f32_e32 vcc
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90 ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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91 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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92 ; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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93 ; GCN-NOT: [[RESULT]]
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94 ; GCN: buffer_store_dword [[RESULT]]
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95 define amdgpu_kernel void @opt_select_i32_or_cmp_f32(i32 addrspace(1)* %out, float %a, float %b, float %c, i32 %x, i32 %y) #0 {
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96 %fcmp0 = fcmp one float %a, %b
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97 %fcmp1 = fcmp one float %a, %c
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98 %or = or i1 %fcmp0, %fcmp1
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99 %select = select i1 %or, i32 %x, i32 %y
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100 store i32 %select, i32 addrspace(1)* %out
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101 ret void
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102 }
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103
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104 ; GCN-LABEL: {{^}}opt_select_i64_or_cmp_i32:
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105 ; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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106 ; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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107 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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108 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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109 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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110 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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111 define amdgpu_kernel void @opt_select_i64_or_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
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112 %icmp0 = icmp ne i32 %a, %b
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113 %icmp1 = icmp ne i32 %a, %c
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114 %or = or i1 %icmp0, %icmp1
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115 %select = select i1 %or, i64 %x, i64 %y
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116 store i64 %select, i64 addrspace(1)* %out
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117 ret void
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118 }
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119
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120 ; GCN-LABEL: {{^}}opt_select_i64_or_cmp_f32:
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121 ; GCN-DAG: v_cmp_lg_f32_e32 vcc,
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122 ; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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123 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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124 ; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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125 ; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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126 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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127 define amdgpu_kernel void @opt_select_i64_or_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 {
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128 %fcmp0 = fcmp one float %a, %b
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129 %fcmp1 = fcmp one float %a, %c
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130 %or = or i1 %fcmp0, %fcmp1
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131 %select = select i1 %or, i64 %x, i64 %y
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132 store i64 %select, i64 addrspace(1)* %out
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133 ret void
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134 }
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135
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136 ; GCN-LABEL: {{^}}regression:
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137 ; GCN: v_cmp_neq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 1.0
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138 ; GCN: v_cmp_neq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 0
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139 ; GCN: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 0
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140
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141 define amdgpu_kernel void @regression(float addrspace(1)* %out, float %c0, float %c1) #0 {
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142 entry:
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143 %cmp0 = fcmp oeq float %c0, 1.0
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144 br i1 %cmp0, label %if0, label %endif
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145
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146 if0:
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147 %cmp1 = fcmp oeq float %c1, 0.0
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148 br i1 %cmp1, label %if1, label %endif
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149
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150 if1:
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151 %cmp2 = xor i1 %cmp1, true
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152 br label %endif
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153
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154 endif:
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155 %tmp0 = phi i1 [ true, %entry ], [ %cmp2, %if1 ], [ false, %if0 ]
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156 %tmp2 = select i1 %tmp0, float 4.0, float 0.0
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157 store float %tmp2, float addrspace(1)* %out
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158 ret void
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159 }
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160
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161 attributes #0 = { nounwind }
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