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150
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1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=FUNC %s
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2 ; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=R600 -check-prefix=FUNC %s
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3
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4 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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5
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6 ; FUNC-LABEL: {{^}}setcc_v2i32:
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7 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
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8 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
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9
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10 ; GCN: v_cmp_eq_u32_e32
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11 ; GCN: v_cmp_eq_u32_e32
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12 define amdgpu_kernel void @setcc_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) #0 {
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13 %result = icmp eq <2 x i32> %a, %b
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14 %sext = sext <2 x i1> %result to <2 x i32>
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15 store <2 x i32> %sext, <2 x i32> addrspace(1)* %out
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16 ret void
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17 }
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18
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19 ; FUNC-LABEL: {{^}}setcc_v4i32:
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20 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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21 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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22 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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23 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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24
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25 ; GCN: v_cmp_eq_u32_e32
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26 ; GCN: v_cmp_eq_u32_e32
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27 ; GCN: v_cmp_eq_u32_e32
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28 ; GCN: v_cmp_eq_u32_e32
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29 define amdgpu_kernel void @setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {
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30 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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31 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
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32 %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
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33 %result = icmp eq <4 x i32> %a, %b
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34 %sext = sext <4 x i1> %result to <4 x i32>
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35 store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
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36 ret void
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37 }
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38
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39 ;;;==========================================================================;;;
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40 ;; Float comparisons
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41 ;;;==========================================================================;;;
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42
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43 ; FUNC-LABEL: {{^}}f32_oeq:
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44 ; R600: SETE_DX10
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45 ; GCN: v_cmp_eq_f32
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46 define amdgpu_kernel void @f32_oeq(i32 addrspace(1)* %out, float %a, float %b) #0 {
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47 entry:
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48 %0 = fcmp oeq float %a, %b
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49 %1 = sext i1 %0 to i32
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50 store i32 %1, i32 addrspace(1)* %out
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51 ret void
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52 }
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53
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54 ; FUNC-LABEL: {{^}}f32_ogt:
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55 ; R600: SETGT_DX10
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56 ; GCN: v_cmp_gt_f32
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57 define amdgpu_kernel void @f32_ogt(i32 addrspace(1)* %out, float %a, float %b) #0 {
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58 entry:
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59 %0 = fcmp ogt float %a, %b
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60 %1 = sext i1 %0 to i32
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61 store i32 %1, i32 addrspace(1)* %out
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62 ret void
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63 }
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64
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65 ; FUNC-LABEL: {{^}}f32_oge:
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66 ; R600: SETGE_DX10
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67 ; GCN: v_cmp_ge_f32
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68 define amdgpu_kernel void @f32_oge(i32 addrspace(1)* %out, float %a, float %b) #0 {
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69 entry:
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70 %0 = fcmp oge float %a, %b
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71 %1 = sext i1 %0 to i32
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72 store i32 %1, i32 addrspace(1)* %out
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73 ret void
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74 }
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75
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76 ; FUNC-LABEL: {{^}}f32_olt:
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77 ; R600: SETGT_DX10
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78 ; GCN: v_cmp_lt_f32
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79 define amdgpu_kernel void @f32_olt(i32 addrspace(1)* %out, float %a, float %b) #0 {
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80 entry:
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81 %0 = fcmp olt float %a, %b
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82 %1 = sext i1 %0 to i32
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83 store i32 %1, i32 addrspace(1)* %out
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84 ret void
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85 }
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86
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87 ; FUNC-LABEL: {{^}}f32_ole:
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88 ; R600: SETGE_DX10
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89 ; GCN: v_cmp_le_f32
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90 define amdgpu_kernel void @f32_ole(i32 addrspace(1)* %out, float %a, float %b) #0 {
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91 entry:
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92 %0 = fcmp ole float %a, %b
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93 %1 = sext i1 %0 to i32
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94 store i32 %1, i32 addrspace(1)* %out
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95 ret void
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96 }
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97
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98 ; FUNC-LABEL: {{^}}f32_one:
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99 ; R600-DAG: SETE_DX10
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100 ; R600-DAG: SETE_DX10
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101 ; R600-DAG: AND_INT
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102 ; R600-DAG: SETNE_DX10
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103 ; R600-DAG: AND_INT
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104 ; R600-DAG: SETNE_INT
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105
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106 ; GCN: v_cmp_lg_f32_e32 vcc
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107 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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108 define amdgpu_kernel void @f32_one(i32 addrspace(1)* %out, float %a, float %b) #0 {
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109 entry:
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110 %0 = fcmp one float %a, %b
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111 %1 = sext i1 %0 to i32
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112 store i32 %1, i32 addrspace(1)* %out
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113 ret void
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114 }
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115
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116 ; FUNC-LABEL: {{^}}f32_ord:
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117 ; R600-DAG: SETE_DX10
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118 ; R600-DAG: SETE_DX10
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119 ; R600-DAG: AND_INT
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120 ; R600-DAG: SETNE_INT
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121 ; GCN: v_cmp_o_f32
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122 define amdgpu_kernel void @f32_ord(i32 addrspace(1)* %out, float %a, float %b) #0 {
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123 entry:
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124 %0 = fcmp ord float %a, %b
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125 %1 = sext i1 %0 to i32
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126 store i32 %1, i32 addrspace(1)* %out
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127 ret void
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128 }
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129
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130 ; FUNC-LABEL: {{^}}f32_ueq:
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131 ; R600-DAG: SETNE_DX10
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132 ; R600-DAG: SETNE_DX10
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133 ; R600-DAG: OR_INT
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134 ; R600-DAG: SETE_DX10
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135 ; R600-DAG: OR_INT
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136 ; R600-DAG: SETNE_INT
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137
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138 ; GCN: v_cmp_nlg_f32_e32 vcc
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139 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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140 define amdgpu_kernel void @f32_ueq(i32 addrspace(1)* %out, float %a, float %b) #0 {
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141 entry:
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142 %0 = fcmp ueq float %a, %b
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143 %1 = sext i1 %0 to i32
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144 store i32 %1, i32 addrspace(1)* %out
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145 ret void
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146 }
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147
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148 ; FUNC-LABEL: {{^}}f32_ugt:
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149 ; R600: SETGE
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150 ; R600: SETE_DX10
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151 ; GCN: v_cmp_nle_f32_e32 vcc
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152 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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153 define amdgpu_kernel void @f32_ugt(i32 addrspace(1)* %out, float %a, float %b) #0 {
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154 entry:
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155 %0 = fcmp ugt float %a, %b
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156 %1 = sext i1 %0 to i32
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157 store i32 %1, i32 addrspace(1)* %out
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158 ret void
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159 }
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160
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161 ; FUNC-LABEL: {{^}}f32_uge:
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162 ; R600: SETGT
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163 ; R600: SETE_DX10
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164
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165 ; GCN: v_cmp_nlt_f32_e32 vcc
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166 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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167 define amdgpu_kernel void @f32_uge(i32 addrspace(1)* %out, float %a, float %b) #0 {
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168 entry:
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169 %0 = fcmp uge float %a, %b
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170 %1 = sext i1 %0 to i32
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171 store i32 %1, i32 addrspace(1)* %out
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172 ret void
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173 }
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174
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175 ; FUNC-LABEL: {{^}}f32_ult:
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176 ; R600: SETGE
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177 ; R600: SETE_DX10
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178
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179 ; GCN: v_cmp_nge_f32_e32 vcc
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180 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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181 define amdgpu_kernel void @f32_ult(i32 addrspace(1)* %out, float %a, float %b) #0 {
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182 entry:
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183 %0 = fcmp ult float %a, %b
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184 %1 = sext i1 %0 to i32
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185 store i32 %1, i32 addrspace(1)* %out
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186 ret void
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187 }
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188
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189 ; FUNC-LABEL: {{^}}f32_ule:
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190 ; R600: SETGT
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191 ; R600: SETE_DX10
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192
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193 ; GCN: v_cmp_ngt_f32_e32 vcc
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194 ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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195 define amdgpu_kernel void @f32_ule(i32 addrspace(1)* %out, float %a, float %b) #0 {
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196 entry:
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197 %0 = fcmp ule float %a, %b
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198 %1 = sext i1 %0 to i32
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199 store i32 %1, i32 addrspace(1)* %out
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200 ret void
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201 }
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202
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203 ; FUNC-LABEL: {{^}}f32_une:
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204 ; R600: SETNE_DX10
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205 ; GCN: v_cmp_neq_f32
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206 define amdgpu_kernel void @f32_une(i32 addrspace(1)* %out, float %a, float %b) #0 {
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207 entry:
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208 %0 = fcmp une float %a, %b
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209 %1 = sext i1 %0 to i32
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210 store i32 %1, i32 addrspace(1)* %out
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211 ret void
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212 }
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213
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214 ; FUNC-LABEL: {{^}}f32_uno:
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215 ; R600: SETNE_DX10
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216 ; R600: SETNE_DX10
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217 ; R600: OR_INT
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218 ; R600: SETNE_INT
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219 ; GCN: v_cmp_u_f32
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220 define amdgpu_kernel void @f32_uno(i32 addrspace(1)* %out, float %a, float %b) #0 {
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221 entry:
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222 %0 = fcmp uno float %a, %b
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223 %1 = sext i1 %0 to i32
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224 store i32 %1, i32 addrspace(1)* %out
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225 ret void
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226 }
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227
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228 ;;;==========================================================================;;;
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229 ;; 32-bit integer comparisons
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230 ;;;==========================================================================;;;
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231
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232 ; FUNC-LABEL: {{^}}i32_eq:
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233 ; R600: SETE_INT
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234 ; GCN: v_cmp_eq_u32
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235 define amdgpu_kernel void @i32_eq(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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236 entry:
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237 %0 = icmp eq i32 %a, %b
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238 %1 = sext i1 %0 to i32
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239 store i32 %1, i32 addrspace(1)* %out
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240 ret void
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241 }
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242
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243 ; FUNC-LABEL: {{^}}i32_ne:
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244 ; R600: SETNE_INT
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245 ; GCN: v_cmp_ne_u32
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246 define amdgpu_kernel void @i32_ne(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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247 entry:
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248 %0 = icmp ne i32 %a, %b
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249 %1 = sext i1 %0 to i32
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250 store i32 %1, i32 addrspace(1)* %out
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251 ret void
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252 }
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253
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254 ; FUNC-LABEL: {{^}}i32_ugt:
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255 ; R600: SETGT_UINT
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256 ; GCN: v_cmp_gt_u32
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257 define amdgpu_kernel void @i32_ugt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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258 entry:
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259 %0 = icmp ugt i32 %a, %b
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260 %1 = sext i1 %0 to i32
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261 store i32 %1, i32 addrspace(1)* %out
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262 ret void
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263 }
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264
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265 ; FUNC-LABEL: {{^}}i32_uge:
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266 ; R600: SETGE_UINT
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267 ; GCN: v_cmp_ge_u32
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268 define amdgpu_kernel void @i32_uge(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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269 entry:
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270 %0 = icmp uge i32 %a, %b
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271 %1 = sext i1 %0 to i32
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272 store i32 %1, i32 addrspace(1)* %out
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273 ret void
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274 }
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275
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276 ; FUNC-LABEL: {{^}}i32_ult:
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277 ; R600: SETGT_UINT
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278 ; GCN: v_cmp_lt_u32
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279 define amdgpu_kernel void @i32_ult(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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280 entry:
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281 %0 = icmp ult i32 %a, %b
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282 %1 = sext i1 %0 to i32
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283 store i32 %1, i32 addrspace(1)* %out
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284 ret void
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285 }
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286
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287 ; FUNC-LABEL: {{^}}i32_ule:
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288 ; R600: SETGE_UINT
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289 ; GCN: v_cmp_le_u32
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290 define amdgpu_kernel void @i32_ule(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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291 entry:
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292 %0 = icmp ule i32 %a, %b
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293 %1 = sext i1 %0 to i32
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294 store i32 %1, i32 addrspace(1)* %out
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295 ret void
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296 }
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297
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298 ; FUNC-LABEL: {{^}}i32_sgt:
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299 ; R600: SETGT_INT
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300 ; GCN: v_cmp_gt_i32
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301 define amdgpu_kernel void @i32_sgt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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302 entry:
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303 %0 = icmp sgt i32 %a, %b
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304 %1 = sext i1 %0 to i32
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305 store i32 %1, i32 addrspace(1)* %out
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306 ret void
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307 }
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308
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309 ; FUNC-LABEL: {{^}}i32_sge:
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310 ; R600: SETGE_INT
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311 ; GCN: v_cmp_ge_i32
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312 define amdgpu_kernel void @i32_sge(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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313 entry:
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314 %0 = icmp sge i32 %a, %b
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315 %1 = sext i1 %0 to i32
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316 store i32 %1, i32 addrspace(1)* %out
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317 ret void
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318 }
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319
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320 ; FUNC-LABEL: {{^}}i32_slt:
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321 ; R600: SETGT_INT
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322 ; GCN: v_cmp_lt_i32
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323 define amdgpu_kernel void @i32_slt(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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324 entry:
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325 %0 = icmp slt i32 %a, %b
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326 %1 = sext i1 %0 to i32
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327 store i32 %1, i32 addrspace(1)* %out
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328 ret void
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329 }
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330
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331 ; FUNC-LABEL: {{^}}i32_sle:
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332 ; R600: SETGE_INT
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333 ; GCN: v_cmp_le_i32
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334 define amdgpu_kernel void @i32_sle(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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335 entry:
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336 %0 = icmp sle i32 %a, %b
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337 %1 = sext i1 %0 to i32
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338 store i32 %1, i32 addrspace(1)* %out
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339 ret void
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340 }
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341
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342 ; FIXME: This does 4 compares
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343 ; FUNC-LABEL: {{^}}v3i32_eq:
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344 ; GCN-DAG: v_cmp_eq_u32
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345 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
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346 ; GCN-DAG: v_cmp_eq_u32
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347 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
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348 ; GCN-DAG: v_cmp_eq_u32
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349 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
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350 ; GCN: s_endpgm
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351 define amdgpu_kernel void @v3i32_eq(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %ptra, <3 x i32> addrspace(1)* %ptrb) #0 {
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352 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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353 %gep.a = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %ptra, i32 %tid
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354 %gep.b = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %ptrb, i32 %tid
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355 %gep.out = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %out, i32 %tid
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356 %a = load <3 x i32>, <3 x i32> addrspace(1)* %gep.a
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357 %b = load <3 x i32>, <3 x i32> addrspace(1)* %gep.b
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358 %cmp = icmp eq <3 x i32> %a, %b
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359 %ext = sext <3 x i1> %cmp to <3 x i32>
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360 store <3 x i32> %ext, <3 x i32> addrspace(1)* %gep.out
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361 ret void
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362 }
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363
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364 ; FUNC-LABEL: {{^}}v3i8_eq:
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365 ; GCN-DAG: v_cmp_eq_u32
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366 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
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367 ; GCN-DAG: v_cmp_eq_u32
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368 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
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369 ; GCN-DAG: v_cmp_eq_u32
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370 ; GCN-DAG: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1,
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371 ; GCN: s_endpgm
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372 define amdgpu_kernel void @v3i8_eq(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %ptra, <3 x i8> addrspace(1)* %ptrb) #0 {
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373 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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374 %gep.a = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %ptra, i32 %tid
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375 %gep.b = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %ptrb, i32 %tid
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376 %gep.out = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %out, i32 %tid
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377 %a = load <3 x i8>, <3 x i8> addrspace(1)* %gep.a
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378 %b = load <3 x i8>, <3 x i8> addrspace(1)* %gep.b
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379 %cmp = icmp eq <3 x i8> %a, %b
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380 %ext = sext <3 x i1> %cmp to <3 x i8>
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381 store <3 x i8> %ext, <3 x i8> addrspace(1)* %gep.out
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382 ret void
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383 }
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384
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385 ; Make sure we don't try to emit i1 setcc ops
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386 ; FUNC-LABEL: setcc-i1
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387 ; GCN: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 1
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388 ; GCN: s_cmp_eq_u32 [[AND]], 0
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389 define amdgpu_kernel void @setcc-i1(i32 %in) #0 {
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390 %and = and i32 %in, 1
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391 %cmp = icmp eq i32 %and, 0
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392 br i1 %cmp, label %endif, label %if
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393 if:
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394 unreachable
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395 endif:
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396 ret void
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397 }
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398
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399 ; FUNC-LABEL: setcc-i1-and-xor
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173
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400 ; GCN-DAG: v_cmp_ge_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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401 ; GCN-DAG: v_cmp_le_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
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402 ; GCN: s_and_b64 s[2:3], [[A]], [[B]]
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150
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403 define amdgpu_kernel void @setcc-i1-and-xor(i32 addrspace(1)* %out, float %cond) #0 {
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404 bb0:
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405 %tmp5 = fcmp oge float %cond, 0.000000e+00
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406 %tmp7 = fcmp ole float %cond, 1.000000e+00
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407 %tmp9 = and i1 %tmp5, %tmp7
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408 %tmp11 = xor i1 %tmp9, 1
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409 br i1 %tmp11, label %bb2, label %bb1
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410
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411 bb1:
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412 store i32 0, i32 addrspace(1)* %out
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413 br label %bb2
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414
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415 bb2:
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416 ret void
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417 }
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418
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419 ; FUNC-LABEL: setcc_v2i32_expand
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420 ; GCN: v_cmp_gt_i32
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421 ; GCN: v_cmp_gt_i32
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422 define amdgpu_kernel void @setcc_v2i32_expand(
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423 <2 x i32> addrspace(1)* %a,
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424 <2 x i32> addrspace(1)* %b,
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425 <2 x i32> addrspace(1)* %c,
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426 <2 x float> addrspace(1)* %r) {
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427 entry:
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428 %a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a
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429 %b.val = load <2 x i32>, <2 x i32> addrspace(1)* %b
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430 %c.val = load <2 x i32>, <2 x i32> addrspace(1)* %c
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431
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432 %icmp.val.1 = icmp sgt <2 x i32> %a.val, <i32 1, i32 1>
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433 %zext.val.1 = zext <2 x i1> %icmp.val.1 to <2 x i32>
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434 %shl.val.1 = shl nuw <2 x i32> %zext.val.1, <i32 31, i32 31>
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435 %xor.val.1 = xor <2 x i32> %shl.val.1, %b.val
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436 %bitcast.val.1 = bitcast <2 x i32> %xor.val.1 to <2 x float>
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437 %icmp.val.2 = icmp sgt <2 x i32> %c.val, <i32 1199570944, i32 1199570944>
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438 %select.val.1 = select <2 x i1> %icmp.val.2, <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> %bitcast.val.1
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439
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440 store <2 x float> %select.val.1, <2 x float> addrspace(1)* %r
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441 ret void
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442 }
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443
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444 ; FUNC-LABEL: setcc_v4i32_expand
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445 ; GCN: v_cmp_gt_i32
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446 ; GCN: v_cmp_gt_i32
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447 ; GCN: v_cmp_gt_i32
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448 ; GCN: v_cmp_gt_i32
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449 define amdgpu_kernel void @setcc_v4i32_expand(
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450 <4 x i32> addrspace(1)* %a,
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451 <4 x i32> addrspace(1)* %b,
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452 <4 x i32> addrspace(1)* %c,
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453 <4 x float> addrspace(1)* %r) {
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454 entry:
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455 %a.val = load <4 x i32>, <4 x i32> addrspace(1)* %a
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456 %b.val = load <4 x i32>, <4 x i32> addrspace(1)* %b
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457 %c.val = load <4 x i32>, <4 x i32> addrspace(1)* %c
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458
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459 %icmp.val.1 = icmp sgt <4 x i32> %a.val, <i32 1, i32 1, i32 1, i32 1>
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460 %zext.val.1 = zext <4 x i1> %icmp.val.1 to <4 x i32>
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461 %shl.val.1 = shl nuw <4 x i32> %zext.val.1, <i32 31, i32 31, i32 31, i32 31>
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462 %xor.val.1 = xor <4 x i32> %shl.val.1, %b.val
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463 %bitcast.val.1 = bitcast <4 x i32> %xor.val.1 to <4 x float>
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464 %icmp.val.2 = icmp sgt <4 x i32> %c.val, <i32 1199570944, i32 1199570944, i32 1199570944, i32 1199570944>
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465 %select.val.1 = select <4 x i1> %icmp.val.2, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %bitcast.val.1
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466
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467 store <4 x float> %select.val.1, <4 x float> addrspace(1)* %r
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468 ret void
|
|
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469 }
|
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470
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471 attributes #0 = { nounwind }
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