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173
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
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3
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4 define amdgpu_kernel void @sext_i16_to_i32_uniform(i32 addrspace(1)* %out, i16 %a, i32 %b) {
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5 ; GCN-LABEL: sext_i16_to_i32_uniform:
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6 ; GCN: ; %bb.0:
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7 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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8 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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9 ; GCN-NEXT: s_mov_b32 s7, 0xf000
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10 ; GCN-NEXT: s_mov_b32 s6, -1
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11 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
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12 ; GCN-NEXT: s_sext_i32_i16 s0, s0
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13 ; GCN-NEXT: s_add_i32 s0, s1, s0
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14 ; GCN-NEXT: v_mov_b32_e32 v0, s0
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15 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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16 ; GCN-NEXT: s_endpgm
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17 %sext = sext i16 %a to i32
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18 %res = add i32 %b, %sext
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19 store i32 %res, i32 addrspace(1)* %out
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20 ret void
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21 }
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22
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23
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24 define amdgpu_kernel void @sext_i16_to_i64_uniform(i64 addrspace(1)* %out, i16 %a, i64 %b) {
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25 ; GCN-LABEL: sext_i16_to_i64_uniform:
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26 ; GCN: ; %bb.0:
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27 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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28 ; GCN-NEXT: s_load_dword s2, s[0:1], 0xb
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29 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
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30 ; GCN-NEXT: s_mov_b32 s7, 0xf000
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31 ; GCN-NEXT: s_mov_b32 s6, -1
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32 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
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33 ; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
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34 ; GCN-NEXT: s_add_u32 s0, s0, s2
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35 ; GCN-NEXT: s_addc_u32 s1, s1, s3
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36 ; GCN-NEXT: v_mov_b32_e32 v0, s0
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37 ; GCN-NEXT: v_mov_b32_e32 v1, s1
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38 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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39 ; GCN-NEXT: s_endpgm
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40 %sext = sext i16 %a to i64
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41 %res = add i64 %b, %sext
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42 store i64 %res, i64 addrspace(1)* %out
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43 ret void
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44 }
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45
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46 define amdgpu_kernel void @sext_i16_to_i32_divergent(i32 addrspace(1)* %out, i16 %a, i32 %b) {
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47 ; GCN-LABEL: sext_i16_to_i32_divergent:
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48 ; GCN: ; %bb.0:
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49 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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50 ; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
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51 ; GCN-NEXT: s_mov_b32 s7, 0xf000
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52 ; GCN-NEXT: s_mov_b32 s6, -1
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53 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
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54 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
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55 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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56 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
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57 ; GCN-NEXT: s_endpgm
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58 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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59 %tid.truncated = trunc i32 %tid to i16
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60 %divergent.a = add i16 %a, %tid.truncated
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61 %sext = sext i16 %divergent.a to i32
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62 store i32 %sext, i32 addrspace(1)* %out
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63 ret void
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64 }
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65
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66
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67 define amdgpu_kernel void @sext_i16_to_i64_divergent(i64 addrspace(1)* %out, i16 %a, i64 %b) {
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68 ; GCN-LABEL: sext_i16_to_i64_divergent:
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69 ; GCN: ; %bb.0:
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70 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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71 ; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
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72 ; GCN-NEXT: s_mov_b32 s7, 0xf000
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73 ; GCN-NEXT: s_mov_b32 s6, -1
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74 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
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75 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0
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76 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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77 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
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78 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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79 ; GCN-NEXT: s_endpgm
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80 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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81 %tid.truncated = trunc i32 %tid to i16
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82 %divergent.a = add i16 %a, %tid.truncated
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83 %sext = sext i16 %divergent.a to i64
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84 store i64 %sext, i64 addrspace(1)* %out
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85 ret void
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86 }
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87
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88 declare i32 @llvm.amdgcn.workitem.id.x() #1
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89
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90 attributes #0 = { nounwind }
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91 attributes #1 = { nounwind readnone speculatable }
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