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150
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1 # RUN: llc -verify-machineinstrs -march=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
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2 # Check that add with carry out isn't incorrectly reduced to e32 when
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3 # the carry out is a virtual register.
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4
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5 # TODO: We should run this test until the end of codegen to make sure
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6 # that the post-RA run does manage to shrink it, but right now the
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7 # resume crashes
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8
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9 ...
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10 # GCN-LABEL: name: shrink_add_vop3{{$}}
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11 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, 0, implicit $exec
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12 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
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13 name: shrink_add_vop3
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14 alignment: 1
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15 exposesReturnsTwice: false
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16 legalized: false
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17 regBankSelected: false
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18 selected: false
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19 tracksRegLiveness: true
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20 registers:
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21 - { id: 0, class: sgpr_64 }
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22 - { id: 1, class: sreg_32_xm0 }
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23 - { id: 2, class: sgpr_32 }
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24 - { id: 3, class: vgpr_32 }
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25 - { id: 4, class: sreg_64_xexec }
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26 - { id: 5, class: sreg_64_xexec }
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27 - { id: 6, class: sreg_32 }
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28 - { id: 7, class: sreg_32 }
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29 - { id: 8, class: sreg_32_xm0 }
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30 - { id: 9, class: sreg_64_xexec }
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31 - { id: 10, class: sreg_32_xm0 }
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32 - { id: 11, class: sreg_32_xm0 }
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33 - { id: 12, class: sgpr_64 }
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34 - { id: 13, class: sgpr_128 }
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35 - { id: 14, class: sreg_32_xm0 }
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36 - { id: 15, class: sreg_64 }
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37 - { id: 16, class: sgpr_128 }
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38 - { id: 17, class: vgpr_32 }
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39 - { id: 18, class: vreg_64 }
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40 - { id: 19, class: vgpr_32 }
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41 - { id: 20, class: vreg_64 }
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42 - { id: 21, class: sreg_32_xm0 }
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43 - { id: 22, class: sreg_32 }
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44 - { id: 23, class: sreg_32 }
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45 - { id: 24, class: vgpr_32 }
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46 - { id: 25, class: vreg_64 }
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47 - { id: 26, class: vgpr_32 }
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48 - { id: 27, class: vreg_64 }
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49 - { id: 28, class: vreg_64 }
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50 - { id: 29, class: vgpr_32 }
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51 liveins:
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52 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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53 - { reg: '$vgpr0', virtual-reg: '%3' }
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54 frameInfo:
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55 isFrameAddressTaken: false
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56 isReturnAddressTaken: false
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57 hasStackMap: false
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58 hasPatchPoint: false
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59 stackSize: 0
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60 offsetAdjustment: 0
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61 maxAlignment: 0
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62 adjustsStack: false
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63 hasCalls: false
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64 maxCallFrameSize: 0
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65 hasOpaqueSPAdjustment: false
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66 hasVAStart: false
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67 hasMustTailInVarArgFunc: false
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68 body: |
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69 bb.0:
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70 liveins: $sgpr0_sgpr1, $vgpr0
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71
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72 %3 = COPY $vgpr0
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73 %0 = COPY $sgpr0_sgpr1
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74 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
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75 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
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76 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
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77 %27 = REG_SEQUENCE %3, 1, %26, 2
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78 %10 = S_MOV_B32 61440
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79 %11 = S_MOV_B32 0
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80 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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81 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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82 %28 = V_LSHL_B64 killed %27, 2, implicit $exec
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83 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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84 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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85 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
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86 %29, %9 = V_ADD_I32_e64 %19, %17, 0, implicit $exec
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87 %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
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88 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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89 S_ENDPGM 0
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90
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91 ...
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92 ---
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93 # GCN-LABEL: name: shrink_sub_vop3{{$}}
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94 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, 0, implicit $exec
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95 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
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96
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97 name: shrink_sub_vop3
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98 alignment: 1
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99 exposesReturnsTwice: false
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100 legalized: false
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101 regBankSelected: false
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102 selected: false
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103 tracksRegLiveness: true
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104 registers:
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105 - { id: 0, class: sgpr_64 }
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106 - { id: 1, class: sreg_32_xm0 }
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107 - { id: 2, class: sgpr_32 }
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108 - { id: 3, class: vgpr_32 }
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109 - { id: 4, class: sreg_64_xexec }
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110 - { id: 5, class: sreg_64_xexec }
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111 - { id: 6, class: sreg_32 }
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112 - { id: 7, class: sreg_32 }
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113 - { id: 8, class: sreg_32_xm0 }
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114 - { id: 9, class: sreg_64_xexec }
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115 - { id: 10, class: sreg_32_xm0 }
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116 - { id: 11, class: sreg_32_xm0 }
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117 - { id: 12, class: sgpr_64 }
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118 - { id: 13, class: sgpr_128 }
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119 - { id: 14, class: sreg_32_xm0 }
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120 - { id: 15, class: sreg_64 }
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121 - { id: 16, class: sgpr_128 }
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122 - { id: 17, class: vgpr_32 }
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123 - { id: 18, class: vreg_64 }
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124 - { id: 19, class: vgpr_32 }
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125 - { id: 20, class: vreg_64 }
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126 - { id: 21, class: sreg_32_xm0 }
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127 - { id: 22, class: sreg_32 }
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128 - { id: 23, class: sreg_32 }
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129 - { id: 24, class: vgpr_32 }
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130 - { id: 25, class: vreg_64 }
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131 - { id: 26, class: vgpr_32 }
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132 - { id: 27, class: vreg_64 }
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133 - { id: 28, class: vreg_64 }
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134 - { id: 29, class: vgpr_32 }
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135 liveins:
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136 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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137 - { reg: '$vgpr0', virtual-reg: '%3' }
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138 frameInfo:
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139 isFrameAddressTaken: false
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140 isReturnAddressTaken: false
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141 hasStackMap: false
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142 hasPatchPoint: false
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143 stackSize: 0
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144 offsetAdjustment: 0
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145 maxAlignment: 0
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146 adjustsStack: false
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147 hasCalls: false
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148 maxCallFrameSize: 0
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149 hasOpaqueSPAdjustment: false
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150 hasVAStart: false
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151 hasMustTailInVarArgFunc: false
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152 body: |
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153 bb.0:
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154 liveins: $sgpr0_sgpr1, $vgpr0
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155
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156 %3 = COPY $vgpr0
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157 %0 = COPY $sgpr0_sgpr1
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158 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
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159 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
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160 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
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161 %27 = REG_SEQUENCE %3, 1, %26, 2
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162 %10 = S_MOV_B32 61440
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163 %11 = S_MOV_B32 0
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164 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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165 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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166 %28 = V_LSHL_B64 killed %27, 2, implicit $exec
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167 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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168 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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169 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
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170 %29, %9 = V_SUB_I32_e64 %19, %17, 0, implicit $exec
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171 %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
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172 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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173 S_ENDPGM 0
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174
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175 ...
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176 ---
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177 # GCN-LABEL: name: shrink_subrev_vop3{{$}}
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178 # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec
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179 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
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180
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181 name: shrink_subrev_vop3
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182 alignment: 1
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183 exposesReturnsTwice: false
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184 legalized: false
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185 regBankSelected: false
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186 selected: false
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187 tracksRegLiveness: true
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188 registers:
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189 - { id: 0, class: sgpr_64 }
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190 - { id: 1, class: sreg_32_xm0 }
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191 - { id: 2, class: sgpr_32 }
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192 - { id: 3, class: vgpr_32 }
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193 - { id: 4, class: sreg_64_xexec }
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194 - { id: 5, class: sreg_64_xexec }
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195 - { id: 6, class: sreg_32 }
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196 - { id: 7, class: sreg_32 }
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197 - { id: 8, class: sreg_32_xm0 }
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198 - { id: 9, class: sreg_64_xexec }
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199 - { id: 10, class: sreg_32_xm0 }
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200 - { id: 11, class: sreg_32_xm0 }
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201 - { id: 12, class: sgpr_64 }
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202 - { id: 13, class: sgpr_128 }
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203 - { id: 14, class: sreg_32_xm0 }
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204 - { id: 15, class: sreg_64 }
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205 - { id: 16, class: sgpr_128 }
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206 - { id: 17, class: vgpr_32 }
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207 - { id: 18, class: vreg_64 }
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208 - { id: 19, class: vgpr_32 }
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209 - { id: 20, class: vreg_64 }
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210 - { id: 21, class: sreg_32_xm0 }
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211 - { id: 22, class: sreg_32 }
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212 - { id: 23, class: sreg_32 }
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213 - { id: 24, class: vgpr_32 }
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214 - { id: 25, class: vreg_64 }
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215 - { id: 26, class: vgpr_32 }
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216 - { id: 27, class: vreg_64 }
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217 - { id: 28, class: vreg_64 }
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218 - { id: 29, class: vgpr_32 }
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219 liveins:
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220 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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221 - { reg: '$vgpr0', virtual-reg: '%3' }
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222 frameInfo:
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223 isFrameAddressTaken: false
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224 isReturnAddressTaken: false
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225 hasStackMap: false
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226 hasPatchPoint: false
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227 stackSize: 0
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228 offsetAdjustment: 0
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229 maxAlignment: 0
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230 adjustsStack: false
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231 hasCalls: false
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232 maxCallFrameSize: 0
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233 hasOpaqueSPAdjustment: false
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234 hasVAStart: false
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235 hasMustTailInVarArgFunc: false
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236 body: |
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237 bb.0:
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238 liveins: $sgpr0_sgpr1, $vgpr0
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239
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240 %3 = COPY $vgpr0
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241 %0 = COPY $sgpr0_sgpr1
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242 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
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243 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
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244 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
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245 %27 = REG_SEQUENCE %3, 1, %26, 2
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246 %10 = S_MOV_B32 61440
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247 %11 = S_MOV_B32 0
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248 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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249 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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250 %28 = V_LSHL_B64 killed %27, 2, implicit $exec
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251 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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252 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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253 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
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254 %29, %9 = V_SUBREV_I32_e64 %19, %17, 0, implicit $exec
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255 %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec
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256 BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
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257 S_ENDPGM 0
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258
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259 ...
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260 ---
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261 # GCN-LABEL: name: check_addc_src2_vop3{{$}}
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262 # GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec
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263 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
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264 name: check_addc_src2_vop3
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265 alignment: 1
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266 exposesReturnsTwice: false
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267 legalized: false
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268 regBankSelected: false
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269 selected: false
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270 tracksRegLiveness: true
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271 registers:
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272 - { id: 0, class: sgpr_64 }
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273 - { id: 1, class: sreg_32_xm0 }
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274 - { id: 2, class: sgpr_32 }
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275 - { id: 3, class: vgpr_32 }
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276 - { id: 4, class: sreg_64_xexec }
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277 - { id: 5, class: sreg_64_xexec }
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278 - { id: 6, class: sreg_32 }
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279 - { id: 7, class: sreg_32 }
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280 - { id: 8, class: sreg_32_xm0 }
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281 - { id: 9, class: sreg_64_xexec }
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282 - { id: 10, class: sreg_32_xm0 }
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283 - { id: 11, class: sreg_32_xm0 }
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284 - { id: 12, class: sgpr_64 }
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285 - { id: 13, class: sgpr_128 }
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286 - { id: 14, class: sreg_32_xm0 }
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287 - { id: 15, class: sreg_64 }
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288 - { id: 16, class: sgpr_128 }
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289 - { id: 17, class: vgpr_32 }
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290 - { id: 18, class: vreg_64 }
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291 - { id: 19, class: vgpr_32 }
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292 - { id: 20, class: vreg_64 }
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293 - { id: 21, class: sreg_32_xm0 }
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294 - { id: 22, class: sreg_32 }
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295 - { id: 23, class: sreg_32 }
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296 - { id: 24, class: vgpr_32 }
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297 - { id: 25, class: vreg_64 }
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298 - { id: 26, class: vgpr_32 }
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299 - { id: 27, class: vreg_64 }
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300 - { id: 28, class: vreg_64 }
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301 - { id: 29, class: vgpr_32 }
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302 liveins:
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303 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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304 - { reg: '$vgpr0', virtual-reg: '%3' }
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305 frameInfo:
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306 isFrameAddressTaken: false
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307 isReturnAddressTaken: false
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308 hasStackMap: false
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309 hasPatchPoint: false
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310 stackSize: 0
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311 offsetAdjustment: 0
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312 maxAlignment: 0
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313 adjustsStack: false
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314 hasCalls: false
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315 maxCallFrameSize: 0
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316 hasOpaqueSPAdjustment: false
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317 hasVAStart: false
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318 hasMustTailInVarArgFunc: false
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319 body: |
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320 bb.0:
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321 liveins: $sgpr0_sgpr1, $vgpr0
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322
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323 %3 = COPY $vgpr0
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324 %0 = COPY $sgpr0_sgpr1
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325 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
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326 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
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327 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
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328 %27 = REG_SEQUENCE %3, 1, %26, 2
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329 %10 = S_MOV_B32 61440
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330 %11 = S_MOV_B32 0
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331 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
332 %13 = REG_SEQUENCE killed %5, 17, %12, 18
|
|
|
333 %28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
|
|
334 %16 = REG_SEQUENCE killed %4, 17, %12, 18
|
|
|
335 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
336 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
|
|
337 %9 = S_MOV_B64 0
|
|
|
338 %29, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec
|
|
|
339 %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
|
|
340 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
341 S_ENDPGM 0
|
|
|
342
|
|
|
343 ...
|
|
|
344 ---
|
|
|
345 # GCN-LABEL: name: shrink_addc_vop3{{$}}
|
|
|
346 # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec
|
|
173
|
347 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
|
150
|
348
|
|
|
349 name: shrink_addc_vop3
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|
|
350 alignment: 1
|
|
|
351 exposesReturnsTwice: false
|
|
|
352 legalized: false
|
|
|
353 regBankSelected: false
|
|
|
354 selected: false
|
|
|
355 tracksRegLiveness: true
|
|
|
356 registers:
|
|
|
357 - { id: 0, class: sgpr_64 }
|
|
|
358 - { id: 1, class: sreg_32_xm0 }
|
|
|
359 - { id: 2, class: sgpr_32 }
|
|
|
360 - { id: 3, class: vgpr_32 }
|
|
|
361 - { id: 4, class: sreg_64_xexec }
|
|
|
362 - { id: 5, class: sreg_64_xexec }
|
|
|
363 - { id: 6, class: sreg_32 }
|
|
|
364 - { id: 7, class: sreg_32 }
|
|
|
365 - { id: 8, class: sreg_32_xm0 }
|
|
|
366 - { id: 9, class: sreg_64 }
|
|
|
367 - { id: 10, class: sreg_32_xm0 }
|
|
|
368 - { id: 11, class: sreg_32_xm0 }
|
|
|
369 - { id: 12, class: sgpr_64 }
|
|
|
370 - { id: 13, class: sgpr_128 }
|
|
|
371 - { id: 14, class: sreg_32_xm0 }
|
|
|
372 - { id: 15, class: sreg_64 }
|
|
|
373 - { id: 16, class: sgpr_128 }
|
|
|
374 - { id: 17, class: vgpr_32 }
|
|
|
375 - { id: 18, class: vreg_64 }
|
|
|
376 - { id: 19, class: vgpr_32 }
|
|
|
377 - { id: 20, class: vreg_64 }
|
|
|
378 - { id: 21, class: sreg_32_xm0 }
|
|
|
379 - { id: 22, class: sreg_32 }
|
|
|
380 - { id: 23, class: sreg_32 }
|
|
|
381 - { id: 24, class: vgpr_32 }
|
|
|
382 - { id: 25, class: vreg_64 }
|
|
|
383 - { id: 26, class: vgpr_32 }
|
|
|
384 - { id: 27, class: vreg_64 }
|
|
|
385 - { id: 28, class: vreg_64 }
|
|
|
386 - { id: 29, class: vgpr_32 }
|
|
|
387 liveins:
|
|
|
388 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
389 - { reg: '$vgpr0', virtual-reg: '%3' }
|
|
|
390 frameInfo:
|
|
|
391 isFrameAddressTaken: false
|
|
|
392 isReturnAddressTaken: false
|
|
|
393 hasStackMap: false
|
|
|
394 hasPatchPoint: false
|
|
|
395 stackSize: 0
|
|
|
396 offsetAdjustment: 0
|
|
|
397 maxAlignment: 0
|
|
|
398 adjustsStack: false
|
|
|
399 hasCalls: false
|
|
|
400 maxCallFrameSize: 0
|
|
|
401 hasOpaqueSPAdjustment: false
|
|
|
402 hasVAStart: false
|
|
|
403 hasMustTailInVarArgFunc: false
|
|
|
404 body: |
|
|
|
405 bb.0:
|
|
|
406 liveins: $sgpr0_sgpr1, $vgpr0
|
|
|
407
|
|
|
408 %3 = COPY $vgpr0
|
|
|
409 %0 = COPY $sgpr0_sgpr1
|
|
|
410 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
411 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
|
|
412 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
|
|
413 %27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
414 %10 = S_MOV_B32 61440
|
|
|
415 %11 = S_MOV_B32 0
|
|
|
416 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
417 %13 = REG_SEQUENCE killed %5, 17, %12, 18
|
|
|
418 %28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
|
|
419 %16 = REG_SEQUENCE killed %4, 17, %12, 18
|
|
|
420 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
421 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
|
|
422 $vcc = S_MOV_B64 0
|
|
|
423 %29, $vcc = V_ADDC_U32_e64 %19, %17, $vcc, 0, implicit $exec
|
|
|
424 %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
|
|
425 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
426 S_ENDPGM 0
|
|
|
427
|
|
|
428 ...
|
|
|
429
|
|
|
430 ---
|
|
|
431 # GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
|
|
|
432 # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec
|
|
|
433 # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
|
|
434 name: shrink_addc_undef_vcc
|
|
|
435 alignment: 1
|
|
|
436 exposesReturnsTwice: false
|
|
|
437 legalized: false
|
|
|
438 regBankSelected: false
|
|
|
439 selected: false
|
|
|
440 tracksRegLiveness: true
|
|
|
441 registers:
|
|
|
442 - { id: 0, class: sgpr_64 }
|
|
|
443 - { id: 1, class: sreg_32_xm0 }
|
|
|
444 - { id: 2, class: sgpr_32 }
|
|
|
445 - { id: 3, class: vgpr_32 }
|
|
|
446 - { id: 4, class: sreg_64_xexec }
|
|
|
447 - { id: 5, class: sreg_64_xexec }
|
|
|
448 - { id: 6, class: sreg_32 }
|
|
|
449 - { id: 7, class: sreg_32 }
|
|
|
450 - { id: 8, class: sreg_32_xm0 }
|
|
|
451 - { id: 9, class: sreg_64 }
|
|
|
452 - { id: 10, class: sreg_32_xm0 }
|
|
|
453 - { id: 11, class: sreg_32_xm0 }
|
|
|
454 - { id: 12, class: sgpr_64 }
|
|
|
455 - { id: 13, class: sgpr_128 }
|
|
|
456 - { id: 14, class: sreg_32_xm0 }
|
|
|
457 - { id: 15, class: sreg_64 }
|
|
|
458 - { id: 16, class: sgpr_128 }
|
|
|
459 - { id: 17, class: vgpr_32 }
|
|
|
460 - { id: 18, class: vreg_64 }
|
|
|
461 - { id: 19, class: vgpr_32 }
|
|
|
462 - { id: 20, class: vreg_64 }
|
|
|
463 - { id: 21, class: sreg_32_xm0 }
|
|
|
464 - { id: 22, class: sreg_32 }
|
|
|
465 - { id: 23, class: sreg_32 }
|
|
|
466 - { id: 24, class: vgpr_32 }
|
|
|
467 - { id: 25, class: vreg_64 }
|
|
|
468 - { id: 26, class: vgpr_32 }
|
|
|
469 - { id: 27, class: vreg_64 }
|
|
|
470 - { id: 28, class: vreg_64 }
|
|
|
471 - { id: 29, class: vgpr_32 }
|
|
|
472 liveins:
|
|
|
473 - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
|
|
|
474 - { reg: '$vgpr0', virtual-reg: '%3' }
|
|
|
475 frameInfo:
|
|
|
476 isFrameAddressTaken: false
|
|
|
477 isReturnAddressTaken: false
|
|
|
478 hasStackMap: false
|
|
|
479 hasPatchPoint: false
|
|
|
480 stackSize: 0
|
|
|
481 offsetAdjustment: 0
|
|
|
482 maxAlignment: 0
|
|
|
483 adjustsStack: false
|
|
|
484 hasCalls: false
|
|
|
485 maxCallFrameSize: 0
|
|
|
486 hasOpaqueSPAdjustment: false
|
|
|
487 hasVAStart: false
|
|
|
488 hasMustTailInVarArgFunc: false
|
|
|
489 body: |
|
|
|
490 bb.0:
|
|
|
491 liveins: $sgpr0_sgpr1, $vgpr0
|
|
|
492
|
|
|
493 %3 = COPY $vgpr0
|
|
|
494 %0 = COPY $sgpr0_sgpr1
|
|
|
495 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0
|
|
|
496 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0, 0
|
|
|
497 %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
|
|
|
498 %27 = REG_SEQUENCE %3, 1, %26, 2
|
|
|
499 %10 = S_MOV_B32 61440
|
|
|
500 %11 = S_MOV_B32 0
|
|
|
501 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
|
502 %13 = REG_SEQUENCE killed %5, 17, %12, 18
|
|
|
503 %28 = V_LSHL_B64 killed %27, 2, implicit $exec
|
|
|
504 %16 = REG_SEQUENCE killed %4, 17, %12, 18
|
|
|
505 %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
506 %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, 0, 0, implicit $exec
|
|
|
507 %29, $vcc = V_ADDC_U32_e64 %19, %17, undef $vcc, 0, implicit $exec
|
|
|
508 %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec
|
|
|
509 BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
|
|
510 S_ENDPGM 0
|
|
|
511
|
|
|
512 ...
|
