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150
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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3
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4 ; GCN-LABEL: {{^}}sitofp_i16_to_f16
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5 ; GCN: buffer_load_{{sshort|ushort}} v[[A_I16:[0-9]+]]
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6
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7 ; SI: v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
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8 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]
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9
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10 ; VI: v_cvt_f16_i16_e32 v[[R_F16:[0-9]+]], v[[A_I16]]
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11
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12 ; GCN: buffer_store_short v[[R_F16]]
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13 ; GCN: s_endpgm
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14 define amdgpu_kernel void @sitofp_i16_to_f16(
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15 half addrspace(1)* %r,
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16 i16 addrspace(1)* %a) {
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17 entry:
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18 %a.val = load i16, i16 addrspace(1)* %a
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19 %r.val = sitofp i16 %a.val to half
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20 store half %r.val, half addrspace(1)* %r
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21 ret void
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22 }
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23
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24 ; GCN-LABEL: {{^}}sitofp_i32_to_f16
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25 ; GCN: buffer_load_dword v[[A_I32:[0-9]+]]
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26 ; GCN: v_cvt_f32_i32_e32 v[[A_I16:[0-9]+]], v[[A_I32]]
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27 ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_I16]]
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28 ; GCN: buffer_store_short v[[R_F16]]
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29 ; GCN: s_endpgm
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30 define amdgpu_kernel void @sitofp_i32_to_f16(
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31 half addrspace(1)* %r,
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32 i32 addrspace(1)* %a) {
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33 entry:
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34 %a.val = load i32, i32 addrspace(1)* %a
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35 %r.val = sitofp i32 %a.val to half
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36 store half %r.val, half addrspace(1)* %r
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37 ret void
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38 }
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39
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40 ; f16 = sitofp i64 is in sint_to_fp.i64.ll
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41
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42 ; GCN-LABEL: {{^}}sitofp_v2i16_to_v2f16
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43 ; GCN: buffer_load_dword
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44
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45 ; SI: v_cvt_f32_i32_e32
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46 ; SI: v_cvt_f32_i32_e32
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47 ; SI: v_cvt_f16_f32_e32
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48 ; SI: v_cvt_f16_f32_e32
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49 ; SI-DAG: v_lshlrev_b32_e32
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50 ; SI: v_or_b32_e32
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51
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52 ; VI-DAG: v_cvt_f16_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
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53 ; VI-DAG: v_cvt_f16_i16_e32
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54 ; VI: v_or_b32_e32
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55
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56 ; GCN: buffer_store_dword
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57 ; GCN: s_endpgm
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58
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59 define amdgpu_kernel void @sitofp_v2i16_to_v2f16(
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60 <2 x half> addrspace(1)* %r,
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61 <2 x i16> addrspace(1)* %a) {
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62 entry:
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63 %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
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64 %r.val = sitofp <2 x i16> %a.val to <2 x half>
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65 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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66 ret void
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67 }
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68
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69 ; GCN-LABEL: {{^}}sitofp_v2i32_to_v2f16
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70 ; GCN: buffer_load_dwordx2
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71
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72 ; SI: v_cvt_f32_i32_e32
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73 ; SI: v_cvt_f32_i32_e32
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74 ; SI: v_cvt_f16_f32_e32
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75 ; SI: v_cvt_f16_f32_e32
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76 ; SI-DAG: v_lshlrev_b32_e32
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77 ; SI: v_or_b32_e32
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78
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79 ; VI-DAG: v_cvt_f32_i32_e32
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80 ; VI-DAG: v_cvt_f32_i32_e32
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81 ; VI-DAG: v_cvt_f16_f32_e32
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82 ; VI-DAG: v_cvt_f16_f32_sdwa
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83 ; VI: v_or_b32_e32
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84
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85 ; GCN: buffer_store_dword
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86 ; GCN: s_endpgm
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87 define amdgpu_kernel void @sitofp_v2i32_to_v2f16(
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88 <2 x half> addrspace(1)* %r,
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89 <2 x i32> addrspace(1)* %a) {
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90 entry:
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91 %a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a
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92 %r.val = sitofp <2 x i32> %a.val to <2 x half>
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93 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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94 ret void
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95 }
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96
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173
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97 ; GCN-LABEL: {{^}}s_sint_to_fp_i1_to_f16:
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150
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98 ; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
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99 ; GCN-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}}
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100 ; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]
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101 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0, [[R_CMP]]
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102 ; GCN-NEXT: v_cvt_f16_f32_e32 [[R_F16:v[0-9]+]], [[RESULT]]
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103 ; GCN: buffer_store_short
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104 ; GCN: s_endpgm
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105 define amdgpu_kernel void @s_sint_to_fp_i1_to_f16(half addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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106 %a = load float, float addrspace(1) * %in0
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107 %b = load float, float addrspace(1) * %in1
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108 %acmp = fcmp oge float %a, 0.000000e+00
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109 %bcmp = fcmp oge float %b, 1.000000e+00
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110 %result = xor i1 %acmp, %bcmp
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111 %fp = sitofp i1 %result to half
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112 store half %fp, half addrspace(1)* %out
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113 ret void
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114 }
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115
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116 ; v2f16 = sitofp v2i64 is in sint_to_fp.i64.ll
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