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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-dce-in-ra=0 -o - %s | FileCheck %s
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3 ; Don't crash when the use of an undefined value is only detected by the
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4 ; register coalescer because it is hidden with subregister insert/extract.
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5 target triple="amdgcn--"
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6
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7 define amdgpu_kernel void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind {
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8 ; CHECK-LABEL: foobar:
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9 ; CHECK: ; %bb.0: ; %entry
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10 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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11 ; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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12 ; CHECK-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 0
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13 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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14 ; CHECK-NEXT: s_mov_b32 s2, -1
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15 ; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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16 ; CHECK-NEXT: v_mov_b32_e32 v0, s4
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17 ; CHECK-NEXT: v_mov_b32_e32 v1, s5
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18 ; CHECK-NEXT: v_mov_b32_e32 v2, s6
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19 ; CHECK-NEXT: v_mov_b32_e32 v3, s7
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20 ; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc
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21 ; CHECK-NEXT: ; %bb.1: ; %ift
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22 ; CHECK-NEXT: s_mov_b32 s4, s5
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23 ; CHECK-NEXT: v_mov_b32_e32 v0, s4
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24 ; CHECK-NEXT: v_mov_b32_e32 v1, s5
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25 ; CHECK-NEXT: v_mov_b32_e32 v2, s6
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26 ; CHECK-NEXT: v_mov_b32_e32 v3, s7
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27 ; CHECK-NEXT: ; %bb.2: ; %ife
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28 ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
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29 ; CHECK-NEXT: s_mov_b32 s3, 0xf000
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30 ; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0
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31 ; CHECK-NEXT: s_endpgm
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32
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33 ; FIXME: The change related to the fact that
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34 ; DetectDeadLanes pass hit "Copy across incompatible class" SGPR -> VGPR in analysis
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35 ; and hence it cannot derive the fact that the vector element in the "ift" block is unused.
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36 ; Such a copies appear because the float4 vectors and their elements in the test are uniform
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37 ; but the PHI node in "ife" block is divergent because of the CF dependency (divergent branch in bb0)
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38 entry:
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39 %v0 = insertelement <4 x float> undef, float %a0, i32 0
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40 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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41 %cnd = icmp eq i32 %tid, 0
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42 br i1 %cnd, label %ift, label %ife
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43
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44 ift:
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45 %v1 = insertelement <4 x float> undef, float %a1, i32 0
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46 br label %ife
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47
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48 ife:
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49 %val = phi <4 x float> [ %v1, %ift ], [ %v0, %entry ]
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50 %v2 = extractelement <4 x float> %val, i32 1
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51 store float %v2, float addrspace(1)* %out, align 4
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52 ret void
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53 }
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54
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55 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
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56
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57 attributes #0 = { nounwind readnone }
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