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150
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1 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032 %s
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2 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1064 %s
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3 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032 %s
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4 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1064 %s
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5 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032,GFX10DEFWAVE %s
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6
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7 ; GCN-LABEL: {{^}}test_vopc_i32:
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8 ; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}}
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9 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, vcc_lo
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10 ; GFX1064: v_cmp_lt_i32_e32 vcc, 0, v{{[0-9]+}}
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11 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, vcc{{$}}
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12 define amdgpu_kernel void @test_vopc_i32(i32 addrspace(1)* %arg) {
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13 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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14 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %lid
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15 %load = load i32, i32 addrspace(1)* %gep, align 4
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16 %cmp = icmp sgt i32 %load, 0
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17 %sel = select i1 %cmp, i32 1, i32 2
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18 store i32 %sel, i32 addrspace(1)* %gep, align 4
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19 ret void
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20 }
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21
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22 ; GCN-LABEL: {{^}}test_vopc_f32:
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23 ; GFX1032: v_cmp_nge_f32_e32 vcc_lo, 0, v{{[0-9]+}}
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24 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, vcc_lo
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25 ; GFX1064: v_cmp_nge_f32_e32 vcc, 0, v{{[0-9]+}}
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26 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, vcc{{$}}
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27 define amdgpu_kernel void @test_vopc_f32(float addrspace(1)* %arg) {
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28 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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29 %gep = getelementptr inbounds float, float addrspace(1)* %arg, i32 %lid
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30 %load = load float, float addrspace(1)* %gep, align 4
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31 %cmp = fcmp ugt float %load, 0.0
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32 %sel = select i1 %cmp, float 1.0, float 2.0
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33 store float %sel, float addrspace(1)* %gep, align 4
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34 ret void
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35 }
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36
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37 ; GCN-LABEL: {{^}}test_vopc_vcmpx:
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38 ; GFX1032: v_cmpx_le_f32_e32 0, v{{[0-9]+}}
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39 ; GFX1064: v_cmpx_le_f32_e32 0, v{{[0-9]+}}
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40 define amdgpu_ps void @test_vopc_vcmpx(float %x) {
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41 %cmp = fcmp oge float %x, 0.0
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42 call void @llvm.amdgcn.kill(i1 %cmp)
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43 ret void
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44 }
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45
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46 ; GCN-LABEL: {{^}}test_vopc_2xf16:
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47 ; GFX1032: v_cmp_le_f16_sdwa [[SC:s[0-9]+]], {{[vs][0-9]+}}, v{{[0-9]+}} src0_sel:WORD_1 src1_sel:DWORD
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48 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 0x3c003c00, v{{[0-9]+}}, [[SC]]
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49 ; GFX1064: v_cmp_le_f16_sdwa [[SC:s\[[0-9:]+\]]], {{[vs][0-9]+}}, v{{[0-9]+}} src0_sel:WORD_1 src1_sel:DWORD
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50 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 0x3c003c00, v{{[0-9]+}}, [[SC]]
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51 define amdgpu_kernel void @test_vopc_2xf16(<2 x half> addrspace(1)* %arg) {
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52 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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53 %gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i32 %lid
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54 %load = load <2 x half>, <2 x half> addrspace(1)* %gep, align 4
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55 %elt = extractelement <2 x half> %load, i32 1
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56 %cmp = fcmp ugt half %elt, 0.0
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57 %sel = select i1 %cmp, <2 x half> <half 1.0, half 1.0>, <2 x half> %load
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58 store <2 x half> %sel, <2 x half> addrspace(1)* %gep, align 4
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59 ret void
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60 }
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61
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62 ; GCN-LABEL: {{^}}test_vopc_class:
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63 ; GFX1032: v_cmp_class_f32_e64 [[C:vcc_lo|s[0-9:]+]], s{{[0-9]+}}, 0x204
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64 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[C]]
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65 ; GFX1064: v_cmp_class_f32_e64 [[C:vcc|s\[[0-9:]+\]]], s{{[0-9]+}}, 0x204
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66 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[C]]{{$}}
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67 define amdgpu_kernel void @test_vopc_class(i32 addrspace(1)* %out, float %x) #0 {
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68 %fabs = tail call float @llvm.fabs.f32(float %x)
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69 %cmp = fcmp oeq float %fabs, 0x7FF0000000000000
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70 %ext = zext i1 %cmp to i32
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71 store i32 %ext, i32 addrspace(1)* %out, align 4
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72 ret void
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73 }
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74
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75 ; GCN-LABEL: {{^}}test_vcmp_vcnd_f16:
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76 ; GFX1032: v_cmp_neq_f16_e64 [[C:vcc_lo|s\[[0-9:]+\]]], 0x7c00, s{{[0-9]+}}
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77 ; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c00, v{{[0-9]+}}, [[C]]
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78
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79 ; GFX1064: v_cmp_neq_f16_e64 [[C:vcc|s\[[0-9:]+\]]], 0x7c00, s{{[0-9]+}}
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80 ; GFX1064: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c00, v{{[0-9]+}}, [[C]]{{$}}
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81 define amdgpu_kernel void @test_vcmp_vcnd_f16(half addrspace(1)* %out, half %x) #0 {
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82 %cmp = fcmp oeq half %x, 0x7FF0000000000000
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83 %sel = select i1 %cmp, half 1.0, half %x
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84 store half %sel, half addrspace(1)* %out, align 2
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85 ret void
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86 }
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87
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88 ; GCN-LABEL: {{^}}test_vop3_cmp_f32_sop_and:
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89 ; GFX1032: v_cmp_nge_f32_e32 vcc_lo, 0, v{{[0-9]+}}
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90 ; GFX1032: v_cmp_nle_f32_e64 [[C2:s[0-9]+]], 1.0, v{{[0-9]+}}
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91 ; GFX1032: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]]
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92 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, [[AND]]
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93 ; GFX1064: v_cmp_nge_f32_e32 vcc, 0, v{{[0-9]+}}
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94 ; GFX1064: v_cmp_nle_f32_e64 [[C2:s\[[0-9:]+\]]], 1.0, v{{[0-9]+}}
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95 ; GFX1064: s_and_b64 [[AND:s\[[0-9:]+\]]], vcc, [[C2]]
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96 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, [[AND]]
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97 define amdgpu_kernel void @test_vop3_cmp_f32_sop_and(float addrspace(1)* %arg) {
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98 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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99 %gep = getelementptr inbounds float, float addrspace(1)* %arg, i32 %lid
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100 %load = load float, float addrspace(1)* %gep, align 4
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101 %cmp = fcmp ugt float %load, 0.0
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102 %cmp2 = fcmp ult float %load, 1.0
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103 %and = and i1 %cmp, %cmp2
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104 %sel = select i1 %and, float 1.0, float 2.0
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105 store float %sel, float addrspace(1)* %gep, align 4
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106 ret void
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107 }
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108
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109 ; GCN-LABEL: {{^}}test_vop3_cmp_i32_sop_xor:
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110 ; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}}
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111 ; GFX1032: v_cmp_gt_i32_e64 [[C2:s[0-9]+]], 1, v{{[0-9]+}}
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112 ; GFX1032: s_xor_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]]
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113 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]]
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114 ; GFX1064: v_cmp_lt_i32_e32 vcc, 0, v{{[0-9]+}}
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115 ; GFX1064: v_cmp_gt_i32_e64 [[C2:s\[[0-9:]+\]]], 1, v{{[0-9]+}}
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116 ; GFX1064: s_xor_b64 [[AND:s\[[0-9:]+\]]], vcc, [[C2]]
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117 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]]
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118 define amdgpu_kernel void @test_vop3_cmp_i32_sop_xor(i32 addrspace(1)* %arg) {
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119 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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120 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %lid
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121 %load = load i32, i32 addrspace(1)* %gep, align 4
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122 %cmp = icmp sgt i32 %load, 0
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123 %cmp2 = icmp slt i32 %load, 1
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124 %xor = xor i1 %cmp, %cmp2
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125 %sel = select i1 %xor, i32 1, i32 2
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126 store i32 %sel, i32 addrspace(1)* %gep, align 4
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127 ret void
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128 }
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129
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130 ; GCN-LABEL: {{^}}test_vop3_cmp_u32_sop_or:
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131 ; GFX1032: v_cmp_lt_u32_e32 vcc_lo, 3, v{{[0-9]+}}
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132 ; GFX1032: v_cmp_gt_u32_e64 [[C2:s[0-9]+]], 2, v{{[0-9]+}}
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133 ; GFX1032: s_or_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]]
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134 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]]
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135 ; GFX1064: v_cmp_lt_u32_e32 vcc, 3, v{{[0-9]+}}
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136 ; GFX1064: v_cmp_gt_u32_e64 [[C2:s\[[0-9:]+\]]], 2, v{{[0-9]+}}
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137 ; GFX1064: s_or_b64 [[AND:s\[[0-9:]+\]]], vcc, [[C2]]
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138 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]]
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139 define amdgpu_kernel void @test_vop3_cmp_u32_sop_or(i32 addrspace(1)* %arg) {
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140 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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141 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %lid
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142 %load = load i32, i32 addrspace(1)* %gep, align 4
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143 %cmp = icmp ugt i32 %load, 3
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144 %cmp2 = icmp ult i32 %load, 2
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145 %or = or i1 %cmp, %cmp2
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146 %sel = select i1 %or, i32 1, i32 2
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147 store i32 %sel, i32 addrspace(1)* %gep, align 4
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148 ret void
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149 }
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150
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151 ; GCN-LABEL: {{^}}test_mask_if:
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152 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
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153 ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
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154 ; GCN: s_cbranch_execz
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155 define amdgpu_kernel void @test_mask_if(i32 addrspace(1)* %arg) #0 {
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156 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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157 %cmp = icmp ugt i32 %lid, 10
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158 br i1 %cmp, label %if, label %endif
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159
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160 if:
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161 store i32 0, i32 addrspace(1)* %arg, align 4
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162 br label %endif
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163
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164 endif:
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165 ret void
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166 }
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167
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168 ; GCN-LABEL: {{^}}test_loop_with_if:
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169 ; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}}
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170 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}}
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171 ; GFX1064: s_or_b64 s[{{[0-9:]+}}], vcc, s[{{[0-9:]+}}]
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172 ; GFX1064: s_andn2_b64 exec, exec, s[{{[0-9:]+}}]
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173 ; GCN: s_cbranch_execz
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174 ; GCN: BB{{.*}}:
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175 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
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176 ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
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177 ; GCN: s_cbranch_execz
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178 ; GCN: ; %bb.{{[0-9]+}}:
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179 ; GCN: BB{{.*}}:
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180 ; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}}
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181 ; GFX1064: s_xor_b64 s[{{[0-9:]+}}], exec, s[{{[0-9:]+}}]
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182 ; GCN: ; %bb.{{[0-9]+}}:
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183 ; GCN: ; %bb.{{[0-9]+}}:
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184 ; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}}
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185 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, s{{[0-9]+}}
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186 ; GFX1064: s_or_b64 exec, exec, s[{{[0-9:]+}}]
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187 ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}}
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188 ; GCN: s_cbranch_execz BB
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189 ; GCN: ; %bb.{{[0-9]+}}:
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190 ; GCN: BB{{.*}}:
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191 ; GCN: s_endpgm
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192 define amdgpu_kernel void @test_loop_with_if(i32 addrspace(1)* %arg) #0 {
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193 bb:
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194 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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195 br label %bb2
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196
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197 bb1:
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198 ret void
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199
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200 bb2:
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201 %tmp3 = phi i32 [ 0, %bb ], [ %tmp15, %bb13 ]
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202 %tmp4 = icmp slt i32 %tmp3, %tmp
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203 br i1 %tmp4, label %bb5, label %bb11
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204
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205 bb5:
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206 %tmp6 = sext i32 %tmp3 to i64
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207 %tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp6
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208 %tmp8 = load i32, i32 addrspace(1)* %tmp7, align 4
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209 %tmp9 = icmp sgt i32 %tmp8, 10
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210 br i1 %tmp9, label %bb10, label %bb11
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211
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212 bb10:
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213 store i32 %tmp, i32 addrspace(1)* %tmp7, align 4
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214 br label %bb13
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215
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216 bb11:
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217 %tmp12 = sdiv i32 %tmp3, 2
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218 br label %bb13
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219
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220 bb13:
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221 %tmp14 = phi i32 [ %tmp3, %bb10 ], [ %tmp12, %bb11 ]
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222 %tmp15 = add nsw i32 %tmp14, 1
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223 %tmp16 = icmp slt i32 %tmp14, 255
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224 br i1 %tmp16, label %bb2, label %bb1
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225 }
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226
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227 ; GCN-LABEL: {{^}}test_loop_with_if_else_break:
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228 ; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo
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229 ; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}}
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230 ; GCN: s_cbranch_execz
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231 ; GCN: ; %bb.{{[0-9]+}}: ; %.preheader
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232 ; GCN: BB{{.*}}:
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233
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234 ; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo
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235 ; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc
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236 ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo
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237 ; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec
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238 ; GCN: global_store_dword
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239 ; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo
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240 ; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec
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241 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]]
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242 ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]]
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243 ; GCN: BB{{.*}}: ; %Flow
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244 ; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]]
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245 ; GFX1064: s_and_b64 [[TMP0:s\[[0-9:]+\]]], exec, [[MASK1]]
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246 ; GFX1032: s_or_b32 [[ACC:s[0-9]+]], [[TMP0]], [[ACC]]
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247 ; GFX1064: s_or_b64 [[ACC:s\[[0-9:]+\]]], [[TMP0]], [[ACC]]
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248 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]]
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249 ; GFX1064: s_andn2_b64 exec, exec, [[ACC]]
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250 ; GCN: s_cbranch_execz
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251 ; GCN: BB{{.*}}:
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252 ; GCN: s_load_dword [[LOAD:s[0-9]+]]
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253 ; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], exec_lo
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254 ; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], exec
|
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255 ; GCN: s_cmp_lt_i32 [[LOAD]], 11
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256 define amdgpu_kernel void @test_loop_with_if_else_break(i32 addrspace(1)* %arg) #0 {
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|
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257 bb:
|
|
|
258 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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|
|
259 %tmp1 = icmp eq i32 %tmp, 0
|
|
|
260 br i1 %tmp1, label %.loopexit, label %.preheader
|
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261
|
|
|
262 .preheader:
|
|
|
263 br label %bb2
|
|
|
264
|
|
|
265 bb2:
|
|
|
266 %tmp3 = phi i32 [ %tmp9, %bb8 ], [ 0, %.preheader ]
|
|
|
267 %tmp4 = zext i32 %tmp3 to i64
|
|
|
268 %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp4
|
|
|
269 %tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
|
|
|
270 %tmp7 = icmp sgt i32 %tmp6, 10
|
|
|
271 br i1 %tmp7, label %bb8, label %.loopexit
|
|
|
272
|
|
|
273 bb8:
|
|
|
274 store i32 %tmp, i32 addrspace(1)* %tmp5, align 4
|
|
|
275 %tmp9 = add nuw nsw i32 %tmp3, 1
|
|
|
276 %tmp10 = icmp ult i32 %tmp9, 256
|
|
|
277 %tmp11 = icmp ult i32 %tmp9, %tmp
|
|
|
278 %tmp12 = and i1 %tmp10, %tmp11
|
|
|
279 br i1 %tmp12, label %bb2, label %.loopexit
|
|
|
280
|
|
|
281 .loopexit:
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|
|
282 ret void
|
|
|
283 }
|
|
|
284
|
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285 ; GCN-LABEL: {{^}}test_addc_vop2b:
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286 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, s{{[0-9]+}}
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287 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}, vcc_lo
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288 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, s{{[0-9]+}}
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289 ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}, vcc{{$}}
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290 define amdgpu_kernel void @test_addc_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 {
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|
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291 bb:
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|
|
292 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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|
293 %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp
|
|
|
294 %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8
|
|
|
295 %tmp5 = add nsw i64 %tmp4, %arg1
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|
|
296 store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8
|
|
|
297 ret void
|
|
|
298 }
|
|
|
299
|
|
|
300 ; GCN-LABEL: {{^}}test_subbrev_vop2b:
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301 ; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
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302 ; GFX1032: v_subrev_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[A0]]{{$}}
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|
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303 ; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
|
|
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304 ; GFX1064: v_subrev_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[A0]]{{$}}
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|
|
305 define amdgpu_kernel void @test_subbrev_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 {
|
|
|
306 bb:
|
|
|
307 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
308 %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp
|
|
|
309 %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8
|
|
|
310 %tmp5 = sub nsw i64 %tmp4, %arg1
|
|
|
311 store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8
|
|
|
312 ret void
|
|
|
313 }
|
|
|
314
|
|
|
315 ; GCN-LABEL: {{^}}test_subb_vop2b:
|
|
|
316 ; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
|
|
|
317 ; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, [[A0]]{{$}}
|
|
|
318 ; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
|
|
|
319 ; GFX1064: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, [[A0]]{{$}}
|
|
|
320 define amdgpu_kernel void @test_subb_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 {
|
|
|
321 bb:
|
|
|
322 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
323 %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp
|
|
|
324 %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8
|
|
|
325 %tmp5 = sub nsw i64 %arg1, %tmp4
|
|
|
326 store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8
|
|
|
327 ret void
|
|
|
328 }
|
|
|
329
|
|
|
330 ; GCN-LABEL: {{^}}test_udiv64:
|
|
|
331 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
332 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo
|
|
|
333 ; GFX1032: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]]
|
|
|
334 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
335 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
336 ; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
337 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo
|
|
|
338 ; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}
|
|
173
|
339 ; GFX1032: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, s{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo
|
|
|
340 ; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo
|
|
150
|
341 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s\[[0-9:]+\]]], v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
342 ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
|
|
|
343 ; GFX1064: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]]
|
|
|
344 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
345 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
346 ; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
347 ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
|
|
|
348 ; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
|
|
173
|
349 ; GFX1064: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, s[{{[0-9:]+}}], {{[vs][0-9]+}}, v{{[0-9]+}}, vcc{{$}}
|
|
|
350 ; GFX1064: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc{{$}}
|
|
150
|
351 define amdgpu_kernel void @test_udiv64(i64 addrspace(1)* %arg) #0 {
|
|
|
352 bb:
|
|
|
353 %tmp = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 1
|
|
|
354 %tmp1 = load i64, i64 addrspace(1)* %tmp, align 8
|
|
|
355 %tmp2 = load i64, i64 addrspace(1)* %arg, align 8
|
|
|
356 %tmp3 = udiv i64 %tmp1, %tmp2
|
|
|
357 %tmp4 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 2
|
|
|
358 store i64 %tmp3, i64 addrspace(1)* %tmp4, align 8
|
|
|
359 ret void
|
|
|
360 }
|
|
|
361
|
|
|
362 ; GCN-LABEL: {{^}}test_div_scale_f32:
|
|
|
363 ; GFX1032: v_div_scale_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
364 ; GFX1064: v_div_scale_f32 v{{[0-9]+}}, s[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
365 define amdgpu_kernel void @test_div_scale_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
|
366 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
367 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
368 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
|
|
369
|
|
|
370 %a = load volatile float, float addrspace(1)* %gep.0, align 4
|
|
|
371 %b = load volatile float, float addrspace(1)* %gep.1, align 4
|
|
|
372
|
|
|
373 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
|
|
|
374 %result0 = extractvalue { float, i1 } %result, 0
|
|
|
375 store float %result0, float addrspace(1)* %out, align 4
|
|
|
376 ret void
|
|
|
377 }
|
|
|
378
|
|
|
379 ; GCN-LABEL: {{^}}test_div_scale_f64:
|
|
|
380 ; GFX1032: v_div_scale_f64 v[{{[0-9:]+}}], s{{[0-9]+}}, v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
|
|
|
381 ; GFX1064: v_div_scale_f64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
|
|
|
382 define amdgpu_kernel void @test_div_scale_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) #0 {
|
|
|
383 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
384 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
|
|
|
385 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
|
|
|
386
|
|
|
387 %a = load volatile double, double addrspace(1)* %gep.0, align 8
|
|
|
388 %b = load volatile double, double addrspace(1)* %gep.1, align 8
|
|
|
389
|
|
|
390 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
|
|
|
391 %result0 = extractvalue { double, i1 } %result, 0
|
|
|
392 store double %result0, double addrspace(1)* %out, align 8
|
|
|
393 ret void
|
|
|
394 }
|
|
|
395
|
|
|
396 ; GCN-LABEL: {{^}}test_mad_i64_i32:
|
|
|
397 ; GFX1032: v_mad_i64_i32 v[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}]
|
|
|
398 ; GFX1064: v_mad_i64_i32 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}]
|
|
|
399 define i64 @test_mad_i64_i32(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
|
|
|
400 %sext0 = sext i32 %arg0 to i64
|
|
|
401 %sext1 = sext i32 %arg1 to i64
|
|
|
402 %mul = mul i64 %sext0, %sext1
|
|
|
403 %mad = add i64 %mul, %arg2
|
|
|
404 ret i64 %mad
|
|
|
405 }
|
|
|
406
|
|
|
407 ; GCN-LABEL: {{^}}test_mad_u64_u32:
|
|
|
408 ; GFX1032: v_mad_u64_u32 v[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}]
|
|
|
409 ; GFX1064: v_mad_u64_u32 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}]
|
|
|
410 define i64 @test_mad_u64_u32(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
|
|
|
411 %sext0 = zext i32 %arg0 to i64
|
|
|
412 %sext1 = zext i32 %arg1 to i64
|
|
|
413 %mul = mul i64 %sext0, %sext1
|
|
|
414 %mad = add i64 %mul, %arg2
|
|
|
415 ret i64 %mad
|
|
|
416 }
|
|
|
417
|
|
|
418 ; GCN-LABEL: {{^}}test_div_fmas_f32:
|
|
|
419 ; GFX1032: v_cmp_eq_u32_e64 vcc_lo,
|
|
|
420 ; GFX1064: v_cmp_eq_u32_e64 vcc,
|
|
|
421 ; GCN: v_div_fmas_f32 v{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
422 define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
|
|
|
423 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
|
|
|
424 store float %result, float addrspace(1)* %out, align 4
|
|
|
425 ret void
|
|
|
426 }
|
|
|
427
|
|
|
428 ; GCN-LABEL: {{^}}test_div_fmas_f64:
|
|
|
429 ; GFX1032: v_cmp_eq_u32_e64 vcc_lo,
|
|
|
430 ; GFX1064: v_cmp_eq_u32_e64 vcc,
|
|
|
431 ; GCN-DAG: v_div_fmas_f64 v[{{[0-9:]+}}], {{[vs]}}[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
|
|
|
432 define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
|
|
|
433 %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
|
|
|
434 store double %result, double addrspace(1)* %out, align 8
|
|
|
435 ret void
|
|
|
436 }
|
|
|
437
|
|
|
438 ; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
|
|
|
439 ; GFX1032: s_mov_b32 [[VCC:vcc_lo]], 0{{$}}
|
|
|
440 ; GFX1064: s_mov_b64 [[VCC:vcc]], 0{{$}}
|
|
|
441 ; GFX1032: s_and_saveexec_b32 [[SAVE:s[0-9]+]], s{{[0-9]+}}{{$}}
|
|
|
442 ; GFX1064: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], s[{{[0-9:]+}}]{{$}}
|
|
|
443
|
|
|
444 ; GCN: load_dword [[LOAD:v[0-9]+]]
|
|
|
445 ; GCN: v_cmp_ne_u32_e32 [[VCC]], 0, [[LOAD]]
|
|
|
446
|
|
|
447 ; GCN: BB{{[0-9_]+}}:
|
|
|
448 ; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE]]
|
|
|
449 ; GFX1064: s_or_b64 exec, exec, [[SAVE]]
|
|
|
450 ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
|
|
|
451 define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) #0 {
|
|
|
452 entry:
|
|
|
453 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
|
454 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
|
|
|
455 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
|
|
|
456 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
|
|
|
457 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
|
|
|
458
|
|
|
459 %a = load float, float addrspace(1)* %gep.a
|
|
|
460 %b = load float, float addrspace(1)* %gep.b
|
|
|
461 %c = load float, float addrspace(1)* %gep.c
|
|
|
462
|
|
|
463 %cmp0 = icmp eq i32 %tid, 0
|
|
|
464 br i1 %cmp0, label %bb, label %exit
|
|
|
465
|
|
|
466 bb:
|
|
|
467 %val = load volatile i32, i32 addrspace(1)* %dummy
|
|
|
468 %cmp1 = icmp ne i32 %val, 0
|
|
|
469 br label %exit
|
|
|
470
|
|
|
471 exit:
|
|
|
472 %cond = phi i1 [false, %entry], [%cmp1, %bb]
|
|
|
473 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone
|
|
|
474 store float %result, float addrspace(1)* %gep.out, align 4
|
|
|
475 ret void
|
|
|
476 }
|
|
|
477
|
|
|
478 ; GCN-LABEL: {{^}}fdiv_f32:
|
|
173
|
479 ; GFX1032: v_div_scale_f32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
480 ; GFX1064: v_div_scale_f32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
|
|
150
|
481 ; GCN: v_rcp_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
482 ; GCN-NOT: vcc
|
|
|
483 ; GCN: v_div_fmas_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
484 define amdgpu_kernel void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) #0 {
|
|
|
485 entry:
|
|
|
486 %fdiv = fdiv float %a, %b
|
|
|
487 store float %fdiv, float addrspace(1)* %out
|
|
|
488 ret void
|
|
|
489 }
|
|
|
490
|
|
|
491 ; GCN-LABEL: {{^}}test_br_cc_f16:
|
|
|
492 ; GFX1032: v_cmp_nlt_f16_e32 vcc_lo,
|
|
|
493 ; GFX1032: s_and_b32 vcc_lo, exec_lo, vcc_lo
|
|
|
494 ; GFX1064: v_cmp_nlt_f16_e32 vcc,
|
|
|
495 ; GFX1064: s_and_b64 vcc, exec, vcc{{$}}
|
|
|
496 ; GCN-NEXT: s_cbranch_vccnz
|
|
|
497 define amdgpu_kernel void @test_br_cc_f16(
|
|
|
498 half addrspace(1)* %r,
|
|
|
499 half addrspace(1)* %a,
|
|
|
500 half addrspace(1)* %b) {
|
|
|
501 entry:
|
|
|
502 %a.val = load half, half addrspace(1)* %a
|
|
|
503 %b.val = load half, half addrspace(1)* %b
|
|
|
504 %fcmp = fcmp olt half %a.val, %b.val
|
|
|
505 br i1 %fcmp, label %one, label %two
|
|
|
506
|
|
|
507 one:
|
|
|
508 store half %a.val, half addrspace(1)* %r
|
|
|
509 ret void
|
|
|
510
|
|
|
511 two:
|
|
|
512 store half %b.val, half addrspace(1)* %r
|
|
|
513 ret void
|
|
|
514 }
|
|
|
515
|
|
|
516 ; GCN-LABEL: {{^}}test_brcc_i1:
|
|
|
517 ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0
|
|
|
518 ; GCN-NEXT: s_cbranch_scc1
|
|
|
519 define amdgpu_kernel void @test_brcc_i1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i1 %val) #0 {
|
|
|
520 %cmp0 = icmp ne i1 %val, 0
|
|
|
521 br i1 %cmp0, label %store, label %end
|
|
|
522
|
|
|
523 store:
|
|
|
524 store i32 222, i32 addrspace(1)* %out
|
|
|
525 ret void
|
|
|
526
|
|
|
527 end:
|
|
|
528 ret void
|
|
|
529 }
|
|
|
530
|
|
|
531 ; GCN-LABEL: {{^}}test_preserve_condition_undef_flag:
|
|
173
|
532 ; GFX1032-DAG: v_cmp_nlt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 1.0
|
|
|
533 ; GFX1032-DAG: v_cmp_ngt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 0
|
|
150
|
534 ; GFX1032: v_cmp_nlt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 1.0
|
|
|
535 ; GFX1032: s_or_b32 [[OR1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
536 ; GFX1032: s_or_b32 [[OR2:s[0-9]+]], [[OR1]], s{{[0-9]+}}
|
|
|
537 ; GFX1032: s_and_b32 vcc_lo, exec_lo, [[OR2]]
|
|
173
|
538 ; GFX1064-DAG: v_cmp_nlt_f32_e64 s[{{[0-9:]+}}], s{{[0-9]+}}, 1.0
|
|
|
539 ; GFX1064-DAG: v_cmp_ngt_f32_e64 s[{{[0-9:]+}}], s{{[0-9]+}}, 0
|
|
150
|
540 ; GFX1064: v_cmp_nlt_f32_e64 s[{{[0-9:]+}}], s{{[0-9]+}}, 1.0
|
|
|
541 ; GFX1064: s_or_b64 [[OR1:s\[[0-9:]+\]]], s[{{[0-9:]+}}], s[{{[0-9:]+}}]
|
|
|
542 ; GFX1064: s_or_b64 [[OR2:s\[[0-9:]+\]]], [[OR1]], s[{{[0-9:]+}}]
|
|
|
543 ; GFX1064: s_and_b64 vcc, exec, [[OR2]]
|
|
|
544 ; GCN: s_cbranch_vccnz
|
|
|
545 define amdgpu_kernel void @test_preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) #0 {
|
|
|
546 bb0:
|
|
|
547 %tmp = icmp sgt i32 %arg1, 4
|
|
|
548 %undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef)
|
|
|
549 %tmp4 = select i1 %undef, float %arg, float 1.000000e+00
|
|
|
550 %tmp5 = fcmp ogt float %arg2, 0.000000e+00
|
|
|
551 %tmp6 = fcmp olt float %arg2, 1.000000e+00
|
|
|
552 %tmp7 = fcmp olt float %arg, %tmp4
|
|
|
553 %tmp8 = and i1 %tmp5, %tmp6
|
|
|
554 %tmp9 = and i1 %tmp8, %tmp7
|
|
|
555 br i1 %tmp9, label %bb1, label %bb2
|
|
|
556
|
|
|
557 bb1:
|
|
|
558 store volatile i32 0, i32 addrspace(1)* undef
|
|
|
559 br label %bb2
|
|
|
560
|
|
|
561 bb2:
|
|
|
562 ret void
|
|
|
563 }
|
|
|
564
|
|
|
565 ; GCN-LABEL: {{^}}test_invert_true_phi_cond_break_loop:
|
|
|
566 ; GFX1032: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, -1
|
|
|
567 ; GFX1032: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
|
|
|
568 ; GFX1064: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1
|
|
|
569 ; GFX1064: s_or_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], s[{{[0-9:]+}}]
|
|
|
570 define amdgpu_kernel void @test_invert_true_phi_cond_break_loop(i32 %arg) #0 {
|
|
|
571 bb:
|
|
|
572 %id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
573 %tmp = sub i32 %id, %arg
|
|
|
574 br label %bb1
|
|
|
575
|
|
|
576 bb1: ; preds = %Flow, %bb
|
|
|
577 %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ]
|
|
|
578 %lsr.iv.next = add i32 %lsr.iv, 1
|
|
|
579 %cmp0 = icmp slt i32 %lsr.iv.next, 0
|
|
|
580 br i1 %cmp0, label %bb4, label %Flow
|
|
|
581
|
|
|
582 bb4: ; preds = %bb1
|
|
|
583 %load = load volatile i32, i32 addrspace(1)* undef, align 4
|
|
|
584 %cmp1 = icmp sge i32 %tmp, %load
|
|
|
585 br label %Flow
|
|
|
586
|
|
|
587 Flow: ; preds = %bb4, %bb1
|
|
|
588 %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ]
|
|
|
589 %tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ]
|
|
|
590 br i1 %tmp3, label %bb1, label %bb9
|
|
|
591
|
|
|
592 bb9: ; preds = %Flow
|
|
|
593 store volatile i32 7, i32 addrspace(3)* undef
|
|
|
594 ret void
|
|
|
595 }
|
|
|
596
|
|
|
597 ; GCN-LABEL: {{^}}test_movrels_extract_neg_offset_vgpr:
|
|
|
598 ; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 1, v{{[0-9]+}}
|
|
|
599 ; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc_lo
|
|
|
600 ; GFX1032: v_cmp_ne_u32_e32 vcc_lo, 2, v{{[0-9]+}}
|
|
|
601 ; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}, vcc_lo
|
|
|
602 ; GFX1032: v_cmp_ne_u32_e32 vcc_lo, 3, v{{[0-9]+}}
|
|
|
603 ; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 3, v{{[0-9]+}}, vcc_lo
|
|
|
604 ; GFX1064: v_cmp_eq_u32_e32 vcc, 1, v{{[0-9]+}}
|
|
|
605 ; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
|
|
|
606 ; GFX1064: v_cmp_ne_u32_e32 vcc, 2, v{{[0-9]+}}
|
|
|
607 ; GFX1064: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}, vcc
|
|
|
608 ; GFX1064: v_cmp_ne_u32_e32 vcc, 3, v{{[0-9]+}}
|
|
|
609 ; GFX1064: v_cndmask_b32_e32 v{{[0-9]+}}, 3, v{{[0-9]+}}, vcc
|
|
|
610 define amdgpu_kernel void @test_movrels_extract_neg_offset_vgpr(i32 addrspace(1)* %out) #0 {
|
|
|
611 entry:
|
|
|
612 %id = call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
613 %index = add i32 %id, -512
|
|
|
614 %value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
|
|
|
615 store i32 %value, i32 addrspace(1)* %out
|
|
|
616 ret void
|
|
|
617 }
|
|
|
618
|
|
|
619 ; GCN-LABEL: {{^}}test_set_inactive:
|
|
|
620 ; GFX1032: s_not_b32 exec_lo, exec_lo
|
|
|
621 ; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 42
|
|
|
622 ; GFX1032: s_not_b32 exec_lo, exec_lo
|
|
|
623 ; GFX1064: s_not_b64 exec, exec{{$}}
|
|
|
624 ; GFX1064: v_mov_b32_e32 {{v[0-9]+}}, 42
|
|
|
625 ; GFX1064: s_not_b64 exec, exec{{$}}
|
|
|
626 define amdgpu_kernel void @test_set_inactive(i32 addrspace(1)* %out, i32 %in) #0 {
|
|
|
627 %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42)
|
|
|
628 store i32 %tmp, i32 addrspace(1)* %out
|
|
|
629 ret void
|
|
|
630 }
|
|
|
631
|
|
|
632 ; GCN-LABEL: {{^}}test_set_inactive_64:
|
|
|
633 ; GFX1032: s_not_b32 exec_lo, exec_lo
|
|
|
634 ; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 0
|
|
|
635 ; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 0
|
|
|
636 ; GFX1032: s_not_b32 exec_lo, exec_lo
|
|
|
637 ; GFX1064: s_not_b64 exec, exec{{$}}
|
|
|
638 ; GFX1064: v_mov_b32_e32 {{v[0-9]+}}, 0
|
|
|
639 ; GFX1064: v_mov_b32_e32 {{v[0-9]+}}, 0
|
|
|
640 ; GFX1064: s_not_b64 exec, exec{{$}}
|
|
|
641 define amdgpu_kernel void @test_set_inactive_64(i64 addrspace(1)* %out, i64 %in) #0 {
|
|
|
642 %tmp = call i64 @llvm.amdgcn.set.inactive.i64(i64 %in, i64 0)
|
|
|
643 store i64 %tmp, i64 addrspace(1)* %out
|
|
|
644 ret void
|
|
|
645 }
|
|
|
646
|
|
|
647 ; GCN-LABEL: {{^}}test_kill_i1_terminator_float:
|
|
|
648 ; GFX1032: s_mov_b32 exec_lo, 0
|
|
|
649 ; GFX1064: s_mov_b64 exec, 0
|
|
|
650 define amdgpu_ps void @test_kill_i1_terminator_float() #0 {
|
|
|
651 call void @llvm.amdgcn.kill(i1 false)
|
|
|
652 ret void
|
|
|
653 }
|
|
|
654
|
|
|
655 ; GCN-LABEL: {{^}}test_kill_i1_terminator_i1:
|
|
|
656 ; GFX1032: s_or_b32 [[OR:s[0-9]+]],
|
|
|
657 ; GFX1032: s_and_b32 exec_lo, exec_lo, [[OR]]
|
|
|
658 ; GFX1064: s_or_b64 [[OR:s\[[0-9:]+\]]],
|
|
|
659 ; GFX1064: s_and_b64 exec, exec, [[OR]]
|
|
|
660 define amdgpu_gs void @test_kill_i1_terminator_i1(i32 %a, i32 %b, i32 %c, i32 %d) #0 {
|
|
|
661 %c1 = icmp slt i32 %a, %b
|
|
|
662 %c2 = icmp slt i32 %c, %d
|
|
|
663 %x = or i1 %c1, %c2
|
|
|
664 call void @llvm.amdgcn.kill(i1 %x)
|
|
|
665 ret void
|
|
|
666 }
|
|
|
667
|
|
|
668 ; GCN-LABEL: {{^}}test_loop_vcc:
|
|
|
669 ; GFX1032: v_cmp_lt_f32_e32 vcc_lo,
|
|
|
670 ; GFX1064: v_cmp_lt_f32_e32 vcc,
|
|
|
671 ; GCN: s_cbranch_vccnz
|
|
|
672 define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) #0 {
|
|
|
673 entry:
|
|
|
674 br label %loop
|
|
|
675
|
|
|
676 loop:
|
|
|
677 %ctr.iv = phi float [ 0.0, %entry ], [ %ctr.next, %body ]
|
|
|
678 %c.iv = phi <4 x float> [ %in, %entry ], [ %c.next, %body ]
|
|
|
679 %cc = fcmp ogt float %ctr.iv, 7.0
|
|
|
680 br i1 %cc, label %break, label %body
|
|
|
681
|
|
|
682 body:
|
|
|
683 %c.iv0 = extractelement <4 x float> %c.iv, i32 0
|
|
|
684 %c.next = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.iv0, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
|
|
|
685 %ctr.next = fadd float %ctr.iv, 2.0
|
|
|
686 br label %loop
|
|
|
687
|
|
|
688 break:
|
|
|
689 ret <4 x float> %c.iv
|
|
|
690 }
|
|
|
691
|
|
|
692 ; GCN-LABEL: {{^}}test_wwm1:
|
|
|
693 ; GFX1032: s_or_saveexec_b32 [[SAVE:s[0-9]+]], -1
|
|
|
694 ; GFX1032: s_mov_b32 exec_lo, [[SAVE]]
|
|
|
695 ; GFX1064: s_or_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], -1
|
|
|
696 ; GFX1064: s_mov_b64 exec, [[SAVE]]
|
|
|
697 define amdgpu_ps float @test_wwm1(i32 inreg %idx0, i32 inreg %idx1, float %src0, float %src1) {
|
|
|
698 main_body:
|
|
|
699 %out = fadd float %src0, %src1
|
|
|
700 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out)
|
|
|
701 ret float %out.0
|
|
|
702 }
|
|
|
703
|
|
|
704 ; GCN-LABEL: {{^}}test_wwm2:
|
|
|
705 ; GFX1032: v_cmp_gt_u32_e32 vcc_lo, 32, v{{[0-9]+}}
|
|
|
706 ; GFX1032: s_and_saveexec_b32 [[SAVE1:s[0-9]+]], vcc_lo
|
|
|
707 ; GFX1032: s_or_saveexec_b32 [[SAVE2:s[0-9]+]], -1
|
|
|
708 ; GFX1032: s_mov_b32 exec_lo, [[SAVE2]]
|
|
|
709 ; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE1]]
|
|
|
710 ; GFX1064: v_cmp_gt_u32_e32 vcc, 32, v{{[0-9]+}}
|
|
|
711 ; GFX1064: s_and_saveexec_b64 [[SAVE1:s\[[0-9:]+\]]], vcc{{$}}
|
|
|
712 ; GFX1064: s_or_saveexec_b64 [[SAVE2:s\[[0-9:]+\]]], -1
|
|
|
713 ; GFX1064: s_mov_b64 exec, [[SAVE2]]
|
|
|
714 ; GFX1064: s_or_b64 exec, exec, [[SAVE1]]
|
|
|
715 define amdgpu_ps float @test_wwm2(i32 inreg %idx) {
|
|
|
716 main_body:
|
|
|
717 ; use mbcnt to make sure the branch is divergent
|
|
|
718 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
|
|
|
719 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
|
|
|
720 %cc = icmp uge i32 %hi, 32
|
|
|
721 br i1 %cc, label %endif, label %if
|
|
|
722
|
|
|
723 if:
|
|
|
724 %src = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx, i32 0, i32 0, i32 0)
|
|
|
725 %out = fadd float %src, %src
|
|
|
726 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out)
|
|
|
727 %out.1 = fadd float %src, %out.0
|
|
|
728 br label %endif
|
|
|
729
|
|
|
730 endif:
|
|
|
731 %out.2 = phi float [ %out.1, %if ], [ 0.0, %main_body ]
|
|
|
732 ret float %out.2
|
|
|
733 }
|
|
|
734
|
|
|
735 ; GCN-LABEL: {{^}}test_wqm1:
|
|
|
736 ; GFX1032: s_mov_b32 [[ORIG:s[0-9]+]], exec_lo
|
|
|
737 ; GFX1032: s_wqm_b32 exec_lo, exec_lo
|
|
|
738 ; GFX1032: s_and_b32 exec_lo, exec_lo, [[ORIG]]
|
|
|
739 ; GFX1064: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec{{$}}
|
|
|
740 ; GFX1064: s_wqm_b64 exec, exec{{$}}
|
|
|
741 ; GFX1064: s_and_b64 exec, exec, [[ORIG]]
|
|
|
742 define amdgpu_ps <4 x float> @test_wqm1(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, <2 x float> %pos) #0 {
|
|
|
743 main_body:
|
|
|
744 %inst23 = extractelement <2 x float> %pos, i32 0
|
|
|
745 %inst24 = extractelement <2 x float> %pos, i32 1
|
|
|
746 %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0)
|
|
|
747 %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0)
|
|
|
748 %inst28 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 1, i32 0, i32 %m0)
|
|
|
749 %inst29 = tail call float @llvm.amdgcn.interp.p2(float %inst28, float %inst24, i32 1, i32 0, i32 %m0)
|
|
|
750 %tex = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %inst26, float %inst29, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0)
|
|
|
751 ret <4 x float> %tex
|
|
|
752 }
|
|
|
753
|
|
|
754 ; GCN-LABEL: {{^}}test_wqm2:
|
|
|
755 ; GFX1032: s_wqm_b32 exec_lo, exec_lo
|
|
|
756 ; GFX1032: s_and_b32 exec_lo, exec_lo, s{{[0-9+]}}
|
|
|
757 ; GFX1064: s_wqm_b64 exec, exec{{$}}
|
|
|
758 ; GFX1064: s_and_b64 exec, exec, s[{{[0-9:]+}}]
|
|
|
759 define amdgpu_ps float @test_wqm2(i32 inreg %idx0, i32 inreg %idx1) #0 {
|
|
|
760 main_body:
|
|
|
761 %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0)
|
|
|
762 %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0)
|
|
|
763 %out = fadd float %src0, %src1
|
|
|
764 %out.0 = bitcast float %out to i32
|
|
|
765 %out.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %out.0)
|
|
|
766 %out.2 = bitcast i32 %out.1 to float
|
|
|
767 ret float %out.2
|
|
|
768 }
|
|
|
769
|
|
|
770 ; GCN-LABEL: {{^}}test_intr_fcmp_i64:
|
|
|
771 ; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}}
|
|
|
772 ; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
|
|
|
773 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
|
|
|
774 ; GFX1064: v_cmp_eq_f32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
|
|
|
775 ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
|
|
|
776 ; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]]
|
|
|
777 ; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[V_LO]]:[[V_HI]]],
|
|
|
778 define amdgpu_kernel void @test_intr_fcmp_i64(i64 addrspace(1)* %out, float %src, float %a) {
|
|
|
779 %temp = call float @llvm.fabs.f32(float %a)
|
|
|
780 %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %src, float %temp, i32 1)
|
|
|
781 store i64 %result, i64 addrspace(1)* %out
|
|
|
782 ret void
|
|
|
783 }
|
|
|
784
|
|
|
785 ; GCN-LABEL: {{^}}test_intr_icmp_i64:
|
|
|
786 ; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}}
|
|
|
787 ; GFX1032-DAG: v_cmp_eq_u32_e64 [[C_LO:vcc_lo|s[0-9]+]], 0x64, {{s[0-9]+}}
|
|
|
788 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[C_LO]]
|
|
|
789 ; GFX1064: v_cmp_eq_u32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], 0x64, {{s[0-9]+}}
|
|
|
790 ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
|
|
|
791 ; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]]
|
|
|
792 ; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[V_LO]]:[[V_HI]]],
|
|
|
793 define amdgpu_kernel void @test_intr_icmp_i64(i64 addrspace(1)* %out, i32 %src) {
|
|
|
794 %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %src, i32 100, i32 32)
|
|
|
795 store i64 %result, i64 addrspace(1)* %out
|
|
|
796 ret void
|
|
|
797 }
|
|
|
798
|
|
|
799 ; GCN-LABEL: {{^}}test_intr_fcmp_i32:
|
|
|
800 ; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
|
|
|
801 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
|
|
|
802 ; GFX1064: v_cmp_eq_f32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}|
|
|
|
803 ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]
|
|
|
804 ; GCN: store_dword v[{{[0-9:]+}}], v[[V_LO]],
|
|
|
805 define amdgpu_kernel void @test_intr_fcmp_i32(i32 addrspace(1)* %out, float %src, float %a) {
|
|
|
806 %temp = call float @llvm.fabs.f32(float %a)
|
|
|
807 %result = call i32 @llvm.amdgcn.fcmp.i32.f32(float %src, float %temp, i32 1)
|
|
|
808 store i32 %result, i32 addrspace(1)* %out
|
|
|
809 ret void
|
|
|
810 }
|
|
|
811
|
|
|
812 ; GCN-LABEL: {{^}}test_intr_icmp_i32:
|
|
|
813 ; GFX1032-DAG: v_cmp_eq_u32_e64 s[[C_LO:[0-9]+]], 0x64, {{s[0-9]+}}
|
|
|
814 ; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}}
|
|
|
815 ; GFX1064: v_cmp_eq_u32_e64 s{{\[}}[[C_LO:[0-9]+]]:{{[0-9]+}}], 0x64, {{s[0-9]+}}
|
|
|
816 ; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}}
|
|
|
817 ; GCN: store_dword v[{{[0-9:]+}}], v[[V_LO]],
|
|
|
818 define amdgpu_kernel void @test_intr_icmp_i32(i32 addrspace(1)* %out, i32 %src) {
|
|
|
819 %result = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %src, i32 100, i32 32)
|
|
|
820 store i32 %result, i32 addrspace(1)* %out
|
|
|
821 ret void
|
|
|
822 }
|
|
|
823
|
|
|
824 ; GCN-LABEL: {{^}}test_wqm_vote:
|
|
|
825 ; GFX1032: v_cmp_neq_f32_e32 vcc_lo, 0
|
|
|
826 ; GFX1032: s_wqm_b32 [[WQM:s[0-9]+]], vcc_lo
|
|
|
827 ; GFX1032: s_and_b32 exec_lo, exec_lo, [[WQM]]
|
|
|
828 ; GFX1064: v_cmp_neq_f32_e32 vcc, 0
|
|
|
829 ; GFX1064: s_wqm_b64 [[WQM:s\[[0-9:]+\]]], vcc{{$}}
|
|
|
830 ; GFX1064: s_and_b64 exec, exec, [[WQM]]
|
|
|
831 define amdgpu_ps void @test_wqm_vote(float %a) {
|
|
|
832 %c1 = fcmp une float %a, 0.0
|
|
|
833 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1)
|
|
|
834 call void @llvm.amdgcn.kill(i1 %c2)
|
|
|
835 ret void
|
|
|
836 }
|
|
|
837
|
|
|
838 ; GCN-LABEL: {{^}}test_branch_true:
|
|
|
839 ; GFX1032: s_and_b32 vcc_lo, exec_lo, -1
|
|
|
840 ; GFX1064: s_and_b64 vcc, exec, -1
|
|
|
841 define amdgpu_kernel void @test_branch_true() #2 {
|
|
|
842 entry:
|
|
|
843 br i1 true, label %for.end, label %for.body.lr.ph
|
|
|
844
|
|
|
845 for.body.lr.ph: ; preds = %entry
|
|
|
846 br label %for.body
|
|
|
847
|
|
|
848 for.body: ; preds = %for.body, %for.body.lr.ph
|
|
|
849 br i1 undef, label %for.end, label %for.body
|
|
|
850
|
|
|
851 for.end: ; preds = %for.body, %entry
|
|
|
852 ret void
|
|
|
853 }
|
|
|
854
|
|
|
855 ; GCN-LABEL: {{^}}test_ps_live:
|
|
|
856 ; GFX1032: s_mov_b32 [[C:s[0-9]+]], exec_lo
|
|
|
857 ; GFX1064: s_mov_b64 [[C:s\[[0-9:]+\]]], exec{{$}}
|
|
|
858 ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[C]]
|
|
|
859 define amdgpu_ps float @test_ps_live() #0 {
|
|
|
860 %live = call i1 @llvm.amdgcn.ps.live()
|
|
|
861 %live.32 = zext i1 %live to i32
|
|
|
862 %r = bitcast i32 %live.32 to float
|
|
|
863 ret float %r
|
|
|
864 }
|
|
|
865
|
|
|
866 ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64:
|
|
|
867 ; GFX1032: v_cmp_neq_f64_e64 [[C:s[0-9]+]], s[{{[0-9:]+}}], 1.0
|
|
|
868 ; GFX1032: s_and_b32 vcc_lo, exec_lo, [[C]]
|
|
|
869 ; GFX1064: v_cmp_neq_f64_e64 [[C:s\[[0-9:]+\]]], s[{{[0-9:]+}}], 1.0
|
|
|
870 ; GFX1064: s_and_b64 vcc, exec, [[C]]
|
|
|
871 define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
|
|
872 entry:
|
|
|
873 %v = load double, double addrspace(1)* %in
|
|
|
874 %cc = fcmp oeq double %v, 1.000000e+00
|
|
|
875 br i1 %cc, label %if, label %endif
|
|
|
876
|
|
|
877 if:
|
|
|
878 %u = fadd double %v, %v
|
|
|
879 br label %endif
|
|
|
880
|
|
|
881 endif:
|
|
|
882 %r = phi double [ %v, %entry ], [ %u, %if ]
|
|
|
883 store double %r, double addrspace(1)* %out
|
|
|
884 ret void
|
|
|
885 }
|
|
|
886
|
|
|
887 ; GCN-LABEL: {{^}}test_vgprblocks_w32_attr:
|
|
|
888 ; Test that the wave size can be overridden in function attributes and that the block size is correct as a result
|
|
|
889 ; GFX10DEFWAVE: ; VGPRBlocks: 1
|
|
|
890 define amdgpu_gs float @test_vgprblocks_w32_attr(float %a, float %b, float %c, float %d, float %e,
|
|
|
891 float %f, float %g, float %h, float %i, float %j, float %k, float %l) #3 {
|
|
|
892 main_body:
|
|
|
893 %s = fadd float %a, %b
|
|
|
894 %s.1 = fadd float %s, %c
|
|
|
895 %s.2 = fadd float %s.1, %d
|
|
|
896 %s.3 = fadd float %s.2, %e
|
|
|
897 %s.4 = fadd float %s.3, %f
|
|
|
898 %s.5 = fadd float %s.4, %g
|
|
|
899 %s.6 = fadd float %s.5, %h
|
|
|
900 %s.7 = fadd float %s.6, %i
|
|
|
901 %s.8 = fadd float %s.7, %j
|
|
|
902 %s.9 = fadd float %s.8, %k
|
|
|
903 %s.10 = fadd float %s.9, %l
|
|
|
904 ret float %s.10
|
|
|
905 }
|
|
|
906
|
|
|
907 ; GCN-LABEL: {{^}}test_vgprblocks_w64_attr:
|
|
|
908 ; Test that the wave size can be overridden in function attributes and that the block size is correct as a result
|
|
|
909 ; GFX10DEFWAVE: ; VGPRBlocks: 2
|
|
|
910 define amdgpu_gs float @test_vgprblocks_w64_attr(float %a, float %b, float %c, float %d, float %e,
|
|
|
911 float %f, float %g, float %h, float %i, float %j, float %k, float %l) #4 {
|
|
|
912 main_body:
|
|
|
913 %s = fadd float %a, %b
|
|
|
914 %s.1 = fadd float %s, %c
|
|
|
915 %s.2 = fadd float %s.1, %d
|
|
|
916 %s.3 = fadd float %s.2, %e
|
|
|
917 %s.4 = fadd float %s.3, %f
|
|
|
918 %s.5 = fadd float %s.4, %g
|
|
|
919 %s.6 = fadd float %s.5, %h
|
|
|
920 %s.7 = fadd float %s.6, %i
|
|
|
921 %s.8 = fadd float %s.7, %j
|
|
|
922 %s.9 = fadd float %s.8, %k
|
|
|
923 %s.10 = fadd float %s.9, %l
|
|
|
924 ret float %s.10
|
|
|
925 }
|
|
|
926
|
|
|
927 ; GCN-LABEL: {{^}}icmp64:
|
|
|
928 ; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v
|
|
|
929 ; GFX1064: v_cmp_eq_u32_e32 vcc, 0, v
|
|
|
930 define amdgpu_kernel void @icmp64(i32 %n, i32 %s) {
|
|
|
931 entry:
|
|
|
932 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
933 %mul4 = mul nsw i32 %s, %n
|
|
|
934 %cmp = icmp slt i32 0, %mul4
|
|
|
935 br label %if.end
|
|
|
936
|
|
|
937 if.end: ; preds = %entry
|
|
|
938 %rem = urem i32 %id, %s
|
|
|
939 %icmp = tail call i64 @llvm.amdgcn.icmp.i64.i32(i32 %rem, i32 0, i32 32)
|
|
|
940 %shr = lshr i64 %icmp, 1
|
|
|
941 %notmask = shl nsw i64 -1, 0
|
|
|
942 %and = and i64 %notmask, %shr
|
|
|
943 %or = or i64 %and, -9223372036854775808
|
|
|
944 %cttz = tail call i64 @llvm.cttz.i64(i64 %or, i1 true)
|
|
|
945 %cast = trunc i64 %cttz to i32
|
|
|
946 %cmp3 = icmp ugt i32 10, %cast
|
|
|
947 %cmp6 = icmp ne i32 %rem, 0
|
|
|
948 %brmerge = or i1 %cmp6, %cmp3
|
|
|
949 br i1 %brmerge, label %if.end2, label %if.then
|
|
|
950
|
|
|
951 if.then: ; preds = %if.end
|
|
|
952 unreachable
|
|
|
953
|
|
|
954 if.end2: ; preds = %if.end
|
|
|
955 ret void
|
|
|
956 }
|
|
|
957
|
|
|
958 ; GCN-LABEL: {{^}}fcmp64:
|
|
|
959 ; GFX1032: v_cmp_eq_f32_e32 vcc_lo, 0, v
|
|
|
960 ; GFX1064: v_cmp_eq_f32_e32 vcc, 0, v
|
|
|
961 define amdgpu_kernel void @fcmp64(float %n, float %s) {
|
|
|
962 entry:
|
|
|
963 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
964 %id.f = uitofp i32 %id to float
|
|
|
965 %mul4 = fmul float %s, %n
|
|
|
966 %cmp = fcmp ult float 0.0, %mul4
|
|
|
967 br label %if.end
|
|
|
968
|
|
|
969 if.end: ; preds = %entry
|
|
|
970 %rem.f = frem float %id.f, %s
|
|
|
971 %fcmp = tail call i64 @llvm.amdgcn.fcmp.i64.f32(float %rem.f, float 0.0, i32 1)
|
|
|
972 %shr = lshr i64 %fcmp, 1
|
|
|
973 %notmask = shl nsw i64 -1, 0
|
|
|
974 %and = and i64 %notmask, %shr
|
|
|
975 %or = or i64 %and, -9223372036854775808
|
|
|
976 %cttz = tail call i64 @llvm.cttz.i64(i64 %or, i1 true)
|
|
|
977 %cast = trunc i64 %cttz to i32
|
|
|
978 %cmp3 = icmp ugt i32 10, %cast
|
|
|
979 %cmp6 = fcmp one float %rem.f, 0.0
|
|
|
980 %brmerge = or i1 %cmp6, %cmp3
|
|
|
981 br i1 %brmerge, label %if.end2, label %if.then
|
|
|
982
|
|
|
983 if.then: ; preds = %if.end
|
|
|
984 unreachable
|
|
|
985
|
|
|
986 if.end2: ; preds = %if.end
|
|
|
987 ret void
|
|
|
988 }
|
|
|
989
|
|
|
990 ; GCN-LABEL: {{^}}icmp32:
|
|
|
991 ; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v
|
|
|
992 ; GFX1064: v_cmp_eq_u32_e32 vcc, 0, v
|
|
|
993 define amdgpu_kernel void @icmp32(i32 %n, i32 %s) {
|
|
|
994 entry:
|
|
|
995 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
996 %mul4 = mul nsw i32 %s, %n
|
|
|
997 %cmp = icmp slt i32 0, %mul4
|
|
|
998 br label %if.end
|
|
|
999
|
|
|
1000 if.end: ; preds = %entry
|
|
|
1001 %rem = urem i32 %id, %s
|
|
|
1002 %icmp = tail call i32 @llvm.amdgcn.icmp.i32.i32(i32 %rem, i32 0, i32 32)
|
|
|
1003 %shr = lshr i32 %icmp, 1
|
|
|
1004 %notmask = shl nsw i32 -1, 0
|
|
|
1005 %and = and i32 %notmask, %shr
|
|
|
1006 %or = or i32 %and, 2147483648
|
|
|
1007 %cttz = tail call i32 @llvm.cttz.i32(i32 %or, i1 true)
|
|
|
1008 %cmp3 = icmp ugt i32 10, %cttz
|
|
|
1009 %cmp6 = icmp ne i32 %rem, 0
|
|
|
1010 %brmerge = or i1 %cmp6, %cmp3
|
|
|
1011 br i1 %brmerge, label %if.end2, label %if.then
|
|
|
1012
|
|
|
1013 if.then: ; preds = %if.end
|
|
|
1014 unreachable
|
|
|
1015
|
|
|
1016 if.end2: ; preds = %if.end
|
|
|
1017 ret void
|
|
|
1018 }
|
|
|
1019
|
|
|
1020 ; GCN-LABEL: {{^}}fcmp32:
|
|
|
1021 ; GFX1032: v_cmp_eq_f32_e32 vcc_lo, 0, v
|
|
|
1022 ; GFX1064: v_cmp_eq_f32_e32 vcc, 0, v
|
|
|
1023 define amdgpu_kernel void @fcmp32(float %n, float %s) {
|
|
|
1024 entry:
|
|
|
1025 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
1026 %id.f = uitofp i32 %id to float
|
|
|
1027 %mul4 = fmul float %s, %n
|
|
|
1028 %cmp = fcmp ult float 0.0, %mul4
|
|
|
1029 br label %if.end
|
|
|
1030
|
|
|
1031 if.end: ; preds = %entry
|
|
|
1032 %rem.f = frem float %id.f, %s
|
|
|
1033 %fcmp = tail call i32 @llvm.amdgcn.fcmp.i32.f32(float %rem.f, float 0.0, i32 1)
|
|
|
1034 %shr = lshr i32 %fcmp, 1
|
|
|
1035 %notmask = shl nsw i32 -1, 0
|
|
|
1036 %and = and i32 %notmask, %shr
|
|
|
1037 %or = or i32 %and, 2147483648
|
|
|
1038 %cttz = tail call i32 @llvm.cttz.i32(i32 %or, i1 true)
|
|
|
1039 %cmp3 = icmp ugt i32 10, %cttz
|
|
|
1040 %cmp6 = fcmp one float %rem.f, 0.0
|
|
|
1041 %brmerge = or i1 %cmp6, %cmp3
|
|
|
1042 br i1 %brmerge, label %if.end2, label %if.then
|
|
|
1043
|
|
|
1044 if.then: ; preds = %if.end
|
|
|
1045 unreachable
|
|
|
1046
|
|
|
1047 if.end2: ; preds = %if.end
|
|
|
1048 ret void
|
|
|
1049 }
|
|
|
1050
|
|
|
1051 declare void @external_void_func_void() #1
|
|
|
1052
|
|
|
1053 ; Test save/restore of VGPR needed for SGPR spilling.
|
|
|
1054
|
|
|
1055 ; GCN-LABEL: {{^}}callee_no_stack_with_call:
|
|
|
1056 ; GCN: s_waitcnt
|
|
|
1057 ; GCN-NEXT: s_waitcnt_vscnt
|
|
|
1058
|
|
|
1059 ; GFX1064-NEXT: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}}
|
|
|
1060 ; GFX1032-NEXT: s_or_saveexec_b32 [[COPY_EXEC0:s[0-9]]], -1{{$}}
|
|
173
|
1061 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
150
|
1062 ; GCN-NEXT: v_nop
|
|
|
1063 ; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC0]]
|
|
|
1064 ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC0]]
|
|
|
1065
|
|
173
|
1066 ; GCN-NEXT: v_writelane_b32 v40, s33, 2
|
|
|
1067 ; GCN: s_mov_b32 s33, s32
|
|
150
|
1068 ; GFX1064: s_add_u32 s32, s32, 0x400
|
|
|
1069 ; GFX1032: s_add_u32 s32, s32, 0x200
|
|
|
1070
|
|
|
1071
|
|
173
|
1072 ; GCN-DAG: v_writelane_b32 v40, s30, 0
|
|
|
1073 ; GCN-DAG: v_writelane_b32 v40, s31, 1
|
|
150
|
1074 ; GCN: s_swappc_b64
|
|
173
|
1075 ; GCN-DAG: v_readlane_b32 s4, v40, 0
|
|
|
1076 ; GCN-DAG: v_readlane_b32 s5, v40, 1
|
|
150
|
1077
|
|
|
1078
|
|
|
1079 ; GFX1064: s_sub_u32 s32, s32, 0x400
|
|
|
1080 ; GFX1032: s_sub_u32 s32, s32, 0x200
|
|
173
|
1081 ; GCN: v_readlane_b32 s33, v40, 2
|
|
150
|
1082 ; GFX1064: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
|
|
|
1083 ; GFX1032: s_or_saveexec_b32 [[COPY_EXEC1:s[0-9]]], -1{{$}}
|
|
173
|
1084 ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
150
|
1085 ; GCN-NEXT: v_nop
|
|
|
1086 ; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
|
|
|
1087 ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC1]]
|
|
|
1088 ; GCN-NEXT: s_waitcnt vmcnt(0)
|
|
|
1089 ; GCN-NEXT: s_setpc_b64
|
|
|
1090 define void @callee_no_stack_with_call() #1 {
|
|
|
1091 call void @external_void_func_void()
|
|
|
1092 ret void
|
|
|
1093 }
|
|
|
1094
|
|
|
1095
|
|
|
1096 declare i32 @llvm.amdgcn.workitem.id.x()
|
|
|
1097 declare float @llvm.fabs.f32(float)
|
|
|
1098 declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1)
|
|
|
1099 declare { double, i1 } @llvm.amdgcn.div.scale.f64(double, double, i1)
|
|
|
1100 declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1)
|
|
|
1101 declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1)
|
|
|
1102 declare i1 @llvm.amdgcn.class.f32(float, i32)
|
|
|
1103 declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32)
|
|
|
1104 declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64)
|
|
|
1105 declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32)
|
|
|
1106 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
|
|
|
1107 declare float @llvm.amdgcn.wwm.f32(float)
|
|
|
1108 declare i32 @llvm.amdgcn.wqm.i32(i32)
|
|
|
1109 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32)
|
|
|
1110 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32)
|
|
|
1111 declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg)
|
|
|
1112 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32)
|
|
|
1113 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32)
|
|
|
1114 declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32)
|
|
|
1115 declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32)
|
|
|
1116 declare i32 @llvm.amdgcn.fcmp.i32.f32(float, float, i32)
|
|
|
1117 declare i32 @llvm.amdgcn.icmp.i32.i32(i32, i32, i32)
|
|
|
1118 declare void @llvm.amdgcn.kill(i1)
|
|
|
1119 declare i1 @llvm.amdgcn.wqm.vote(i1)
|
|
|
1120 declare i1 @llvm.amdgcn.ps.live()
|
|
|
1121 declare i64 @llvm.cttz.i64(i64, i1)
|
|
|
1122 declare i32 @llvm.cttz.i32(i32, i1)
|
|
|
1123
|
|
|
1124 attributes #0 = { nounwind readnone speculatable }
|
|
|
1125 attributes #1 = { nounwind }
|
|
|
1126 attributes #2 = { nounwind readnone optnone noinline }
|
|
|
1127 attributes #3 = { "target-features"="+wavefrontsize32" }
|
|
|
1128 attributes #4 = { "target-features"="+wavefrontsize64" }
|
