Mercurial > hg > CbC > CbC_llvm

annotate lib/Target/ARM/README-Thumb.txt @ 131:f476a9ba4795

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http://llvm.org/svn/llvm-project/compiler-rt/trunk compiler-rt
author mir3636
date Fri, 16 Feb 2018 21:02:11 +0900
parents 1172e4bd9c6f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 //===---------------------------------------------------------------------===//
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2 // Random ideas for the ARM backend (Thumb specific).
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3 //===---------------------------------------------------------------------===//
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4
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5 * Add support for compiling functions in both ARM and Thumb mode, then taking
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 the smallest.
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7
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8 * Add support for compiling individual basic blocks in thumb mode, when in a
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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9 larger ARM function. This can be used for presumed cold code, like paths
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parents:
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10 to abort (failure path of asserts), EH handling code, etc.
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11
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12 * Thumb doesn't have normal pre/post increment addressing modes, but you can
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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13 load/store 32-bit integers with pre/postinc by using load/store multiple
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parents:
diff changeset
14 instrs with a single register.
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15
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 * Make better use of high registers r8, r10, r11, r12 (ip). Some variants of add
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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17 and cmp instructions can use high registers. Also, we can use them as
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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18 temporaries to spill values into.
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19
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parents:
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20 * In thumb mode, short, byte, and bool preferred alignments are currently set
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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21 to 4 to accommodate ISA restriction (i.e. add sp, #imm, imm must be multiple
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22 of 4).
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23
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24 //===---------------------------------------------------------------------===//
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25
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26 Potential jumptable improvements:
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27
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28 * If we know function size is less than (1 << 16) * 2 bytes, we can use 16-bit
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29 jumptable entries (e.g. (L1 - L2) >> 1). Or even smaller entries if the
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30 function is even smaller. This also applies to ARM.
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31
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32 * Thumb jumptable codegen can improve given some help from the assembler. This
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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33 is what we generate right now:
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34
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35 .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
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36 LPCRELL0:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37 mov r1, #PCRELV0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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38 add r1, pc
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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39 ldr r0, [r0, r1]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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40 mov pc, r0
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41 .align 2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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42 LJTI1_0_0:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43 .long LBB1_3
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44 ...
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45
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46 Note there is another pc relative add that we can take advantage of.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 add r1, pc, #imm_8 * 4
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48
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49 We should be able to generate:
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parents:
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50
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51 LPCRELL0:
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parents:
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52 add r1, LJTI1_0_0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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53 ldr r0, [r0, r1]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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54 mov pc, r0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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55 .align 2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 LJTI1_0_0:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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57 .long LBB1_3
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parents:
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58
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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59 if the assembler can translate the add to:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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60 add r1, pc, #((LJTI1_0_0-(LPCRELL0+4))&0xfffffffc)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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61
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parents:
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62 Note the assembler also does something similar to constpool load:
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63 LPCRELL0:
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64 ldr r0, LCPI1_0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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65 =>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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66 ldr r0, pc, #((LCPI1_0-(LPCRELL0+4))&0xfffffffc)
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67
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68
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69 //===---------------------------------------------------------------------===//
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70
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71 We compile the following:
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parents:
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72
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parents:
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73 define i16 @func_entry_2E_ce(i32 %i) {
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parents:
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74 switch i32 %i, label %bb12.exitStub [
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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75 i32 0, label %bb4.exitStub
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76 i32 1, label %bb9.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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77 i32 2, label %bb4.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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78 i32 3, label %bb4.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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79 i32 7, label %bb9.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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80 i32 8, label %bb.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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81 i32 9, label %bb9.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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82 ]
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parents:
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83
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84 bb12.exitStub:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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85 ret i16 0
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parents:
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86
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87 bb4.exitStub:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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88 ret i16 1
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parents:
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89
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90 bb9.exitStub:
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parents:
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91 ret i16 2
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parents:
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92
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93 bb.exitStub:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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94 ret i16 3
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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95 }
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parents:
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96
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parents:
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97 into:
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parents:
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98
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parents:
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99 _func_entry_2E_ce:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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100 mov r2, #1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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101 lsl r2, r0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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102 cmp r0, #9
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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103 bhi LBB1_4 @bb12.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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104 LBB1_1: @newFuncRoot
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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105 mov r1, #13
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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106 tst r2, r1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
107 bne LBB1_5 @bb4.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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108 LBB1_2: @newFuncRoot
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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109 ldr r1, LCPI1_0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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110 tst r2, r1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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111 bne LBB1_6 @bb9.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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112 LBB1_3: @newFuncRoot
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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113 mov r1, #1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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114 lsl r1, r1, #8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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115 tst r2, r1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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116 bne LBB1_7 @bb.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
117 LBB1_4: @bb12.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
118 mov r0, #0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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119 bx lr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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120 LBB1_5: @bb4.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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121 mov r0, #1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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122 bx lr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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123 LBB1_6: @bb9.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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124 mov r0, #2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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125 bx lr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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126 LBB1_7: @bb.exitStub
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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127 mov r0, #3
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 bx lr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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129 LBB1_8:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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130 .align 2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 LCPI1_0:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 .long 642
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 gcc compiles to:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 cmp r0, #9
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 @ lr needed for prologue
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 bhi L2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 ldr r3, L11
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 mov r2, #1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 mov r1, r2, asl r0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 ands r0, r3, r2, asl r0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 movne r0, #2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 bxne lr
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 tst r1, #13
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 beq L9
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 L3:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 mov r0, r2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 bx lr
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 L9:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 tst r1, #256
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 movne r0, #3
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 bxne lr
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 L2:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 mov r0, #0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 bx lr
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 L12:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 .align 2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 L11:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 .long 642
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
162
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
163
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 GCC is doing a couple of clever things here:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 1. It is predicating one of the returns. This isn't a clear win though: in
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 cases where that return isn't taken, it is replacing one condbranch with
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 two 'ne' predicated instructions.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 2. It is sinking the shift of "1 << i" into the tst, and using ands instead of
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 tst. This will probably require whole function isel.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 3. GCC emits:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 tst r1, #256
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 we emit:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 mov r1, #1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 lsl r1, r1, #8
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 tst r2, r1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
176
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
178
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 When spilling in thumb mode and the sp offset is too large to fit in the ldr /
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 str offset field, we load the offset from a constpool entry and add it to sp:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
181
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 ldr r2, LCPI
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 add r2, sp
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 ldr r2, [r2]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 These instructions preserve the condition code which is important if the spill
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 is between a cmp and a bcc instruction. However, we can use the (potentially)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 cheaper sequnce if we know it's ok to clobber the condition register.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
189
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 add r2, sp, #255 * 4
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 add r2, #132
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 ldr r2, [r2, #7 * 4]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
193
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 This is especially bad when dynamic alloca is used. The all fixed size stack
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 objects are referenced off the frame pointer with negative offsets. See
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 oggenc for an example.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
199
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
200 Poor codegen test/CodeGen/ARM/select.ll f7:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
201
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 ldr r5, LCPI1_0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 LPC0:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 add r5, pc
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 ldr r6, LCPI1_1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 ldr r2, LCPI1_2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
207 mov r3, r6
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 mov lr, pc
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 bx r5
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
210
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
212
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 Make register allocator / spiller smarter so we can re-materialize "mov r, imm",
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 etc. Almost all Thumb instructions clobber condition code.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
215
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
217
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
218 Thumb load / store address mode offsets are scaled. The values kept in the
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
219 instruction operands are pre-scale values. This probably ought to be changed
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
220 to avoid extra work when we convert Thumb2 instructions to Thumb1 instructions.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
221
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
222 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
223
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
224 We need to make (some of the) Thumb1 instructions predicable. That will allow
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
225 shrinking of predicated Thumb2 instructions. To allow this, we need to be able
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
226 to toggle the 's' bit since they do not set CPSR when they are inside IT blocks.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
227
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
228 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
229
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
231
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
232 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
233
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 Thumb1 immediate field sometimes keep pre-scaled values. See
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
235 ThumbRegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
236 Thumb2.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
237
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
239
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 Rather than having tBR_JTr print a ".align 2" and constant island pass pad it,
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
241 add a target specific ALIGN instruction instead. That way, getInstSizeInBytes
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 won't have to over-estimate. It can also be used for loop alignment pass.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
243
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 //===---------------------------------------------------------------------===//
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
245
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 We generate conditional code for icmp when we don't need to. This code:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
247
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
248 int foo(int s) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 return s == 1;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 produces:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 foo:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
255 cmp r0, #1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
256 mov.w r0, #0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
257 it eq
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 moveq r0, #1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
259 bx lr
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
260
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
261 when it could use subs + adcs. This is GCC PR46975.