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1 //===- BitTracker.h ---------------------------------------------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8
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9 #ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
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10 #define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
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11
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12 #include "llvm/ADT/DenseSet.h"
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13 #include "llvm/ADT/SetVector.h"
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14 #include "llvm/ADT/SmallVector.h"
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15 #include "llvm/CodeGen/MachineInstr.h"
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16 #include "llvm/CodeGen/MachineOperand.h"
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17 #include <cassert>
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18 #include <cstdint>
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19 #include <map>
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20 #include <queue>
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21 #include <set>
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22 #include <utility>
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23
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24 namespace llvm {
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25
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26 class BitVector;
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27 class ConstantInt;
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28 class MachineRegisterInfo;
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29 class MachineBasicBlock;
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30 class MachineFunction;
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31 class raw_ostream;
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32 class TargetRegisterClass;
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33 class TargetRegisterInfo;
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34
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35 struct BitTracker {
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36 struct BitRef;
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37 struct RegisterRef;
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38 struct BitValue;
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39 struct BitMask;
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40 struct RegisterCell;
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41 struct MachineEvaluator;
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42
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43 using BranchTargetList = SetVector<const MachineBasicBlock *>;
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44 using CellMapType = std::map<unsigned, RegisterCell>;
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45
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46 BitTracker(const MachineEvaluator &E, MachineFunction &F);
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47 ~BitTracker();
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48
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49 void run();
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50 void trace(bool On = false) { Trace = On; }
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51 bool has(unsigned Reg) const;
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52 const RegisterCell &lookup(unsigned Reg) const;
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53 RegisterCell get(RegisterRef RR) const;
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54 void put(RegisterRef RR, const RegisterCell &RC);
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55 void subst(RegisterRef OldRR, RegisterRef NewRR);
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56 bool reached(const MachineBasicBlock *B) const;
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57 void visit(const MachineInstr &MI);
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58
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59 void print_cells(raw_ostream &OS) const;
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60
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61 private:
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62 void visitPHI(const MachineInstr &PI);
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63 void visitNonBranch(const MachineInstr &MI);
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64 void visitBranchesFrom(const MachineInstr &BI);
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207
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65 void visitUsesOf(Register Reg);
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150
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66
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67 using CFGEdge = std::pair<int, int>;
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68 using EdgeSetType = std::set<CFGEdge>;
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69 using InstrSetType = std::set<const MachineInstr *>;
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70 using EdgeQueueType = std::queue<CFGEdge>;
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71
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72 // Priority queue of instructions using modified registers, ordered by
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73 // their relative position in a basic block.
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74 struct UseQueueType {
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75 UseQueueType() : Uses(Dist) {}
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76
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77 unsigned size() const {
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78 return Uses.size();
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79 }
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80 bool empty() const {
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81 return size() == 0;
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82 }
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83 MachineInstr *front() const {
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84 return Uses.top();
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85 }
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86 void push(MachineInstr *MI) {
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87 if (Set.insert(MI).second)
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88 Uses.push(MI);
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89 }
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90 void pop() {
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91 Set.erase(front());
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92 Uses.pop();
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93 }
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94 void reset() {
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95 Dist.clear();
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96 }
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97 private:
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98 struct Cmp {
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99 Cmp(DenseMap<const MachineInstr*,unsigned> &Map) : Dist(Map) {}
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100 bool operator()(const MachineInstr *MI, const MachineInstr *MJ) const;
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101 DenseMap<const MachineInstr*,unsigned> &Dist;
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102 };
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103 std::priority_queue<MachineInstr*, std::vector<MachineInstr*>, Cmp> Uses;
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104 DenseSet<const MachineInstr*> Set; // Set to avoid adding duplicate entries.
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105 DenseMap<const MachineInstr*,unsigned> Dist;
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106 };
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107
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108 void reset();
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109 void runEdgeQueue(BitVector &BlockScanned);
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110 void runUseQueue();
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111
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112 const MachineEvaluator &ME;
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113 MachineFunction &MF;
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114 MachineRegisterInfo &MRI;
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115 CellMapType ⤅
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116
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117 EdgeSetType EdgeExec; // Executable flow graph edges.
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118 InstrSetType InstrExec; // Executable instructions.
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119 UseQueueType UseQ; // Work queue of register uses.
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120 EdgeQueueType FlowQ; // Work queue of CFG edges.
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121 DenseSet<unsigned> ReachedBB; // Cache of reached blocks.
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122 bool Trace; // Enable tracing for debugging.
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123 };
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124
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125 // Abstraction of a reference to bit at position Pos from a register Reg.
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126 struct BitTracker::BitRef {
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127 BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {}
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128
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129 bool operator== (const BitRef &BR) const {
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130 // If Reg is 0, disregard Pos.
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131 return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
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132 }
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133
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134 Register Reg;
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135 uint16_t Pos;
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136 };
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137
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138 // Abstraction of a register reference in MachineOperand. It contains the
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139 // register number and the subregister index.
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207
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140 // FIXME: Consolidate duplicate definitions of RegisterRef
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150
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141 struct BitTracker::RegisterRef {
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207
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142 RegisterRef(Register R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
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150
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143 RegisterRef(const MachineOperand &MO)
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144 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
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145
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207
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146 Register Reg;
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147 unsigned Sub;
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150
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148 };
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149
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150 // Value that a single bit can take. This is outside of the context of
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151 // any register, it is more of an abstraction of the two-element set of
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152 // possible bit values. One extension here is the "Ref" type, which
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153 // indicates that this bit takes the same value as the bit described by
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154 // RefInfo.
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155 struct BitTracker::BitValue {
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156 enum ValueType {
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157 Top, // Bit not yet defined.
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158 Zero, // Bit = 0.
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159 One, // Bit = 1.
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160 Ref // Bit value same as the one described in RefI.
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161 // Conceptually, there is no explicit "bottom" value: the lattice's
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162 // bottom will be expressed as a "ref to itself", which, in the context
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163 // of registers, could be read as "this value of this bit is defined by
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164 // this bit".
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165 // The ordering is:
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166 // x <= Top,
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167 // Self <= x, where "Self" is "ref to itself".
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168 // This makes the value lattice different for each virtual register
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169 // (even for each bit in the same virtual register), since the "bottom"
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170 // for one register will be a simple "ref" for another register.
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171 // Since we do not store the "Self" bit and register number, the meet
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172 // operation will need to take it as a parameter.
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173 //
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174 // In practice there is a special case for values that are not associa-
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175 // ted with any specific virtual register. An example would be a value
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176 // corresponding to a bit of a physical register, or an intermediate
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177 // value obtained in some computation (such as instruction evaluation).
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178 // Such cases are identical to the usual Ref type, but the register
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179 // number is 0. In such case the Pos field of the reference is ignored.
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180 //
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181 // What is worthy of notice is that in value V (that is a "ref"), as long
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182 // as the RefI.Reg is not 0, it may actually be the same register as the
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183 // one in which V will be contained. If the RefI.Pos refers to the posi-
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184 // tion of V, then V is assumed to be "bottom" (as a "ref to itself"),
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185 // otherwise V is taken to be identical to the referenced bit of the
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186 // same register.
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187 // If RefI.Reg is 0, however, such a reference to the same register is
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188 // not possible. Any value V that is a "ref", and whose RefI.Reg is 0
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189 // is treated as "bottom".
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190 };
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191 ValueType Type;
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192 BitRef RefI;
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193
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194 BitValue(ValueType T = Top) : Type(T) {}
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195 BitValue(bool B) : Type(B ? One : Zero) {}
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196 BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {}
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197
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198 bool operator== (const BitValue &V) const {
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199 if (Type != V.Type)
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200 return false;
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201 if (Type == Ref && !(RefI == V.RefI))
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202 return false;
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203 return true;
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204 }
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205 bool operator!= (const BitValue &V) const {
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206 return !operator==(V);
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207 }
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208
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209 bool is(unsigned T) const {
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210 assert(T == 0 || T == 1);
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211 return T == 0 ? Type == Zero
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212 : (T == 1 ? Type == One : false);
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213 }
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214
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215 // The "meet" operation is the "." operation in a semilattice (L, ., T, B):
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216 // (1) x.x = x
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217 // (2) x.y = y.x
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218 // (3) x.(y.z) = (x.y).z
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219 // (4) x.T = x (i.e. T = "top")
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220 // (5) x.B = B (i.e. B = "bottom")
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221 //
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222 // This "meet" function will update the value of the "*this" object with
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223 // the newly calculated one, and return "true" if the value of *this has
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224 // changed, and "false" otherwise.
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225 // To prove that it satisfies the conditions (1)-(5), it is sufficient
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226 // to show that a relation
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227 // x <= y <=> x.y = x
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228 // defines a partial order (i.e. that "meet" is same as "infimum").
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229 bool meet(const BitValue &V, const BitRef &Self) {
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230 // First, check the cases where there is nothing to be done.
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231 if (Type == Ref && RefI == Self) // Bottom.meet(V) = Bottom (i.e. This)
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232 return false;
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233 if (V.Type == Top) // This.meet(Top) = This
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234 return false;
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235 if (*this == V) // This.meet(This) = This
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236 return false;
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237
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238 // At this point, we know that the value of "this" will change.
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239 // If it is Top, it will become the same as V, otherwise it will
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240 // become "bottom" (i.e. Self).
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241 if (Type == Top) {
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242 Type = V.Type;
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243 RefI = V.RefI; // This may be irrelevant, but copy anyway.
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244 return true;
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245 }
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246 // Become "bottom".
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247 Type = Ref;
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248 RefI = Self;
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249 return true;
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250 }
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251
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252 // Create a reference to the bit value V.
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253 static BitValue ref(const BitValue &V);
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254 // Create a "self".
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255 static BitValue self(const BitRef &Self = BitRef());
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256
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257 bool num() const {
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258 return Type == Zero || Type == One;
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259 }
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260
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261 operator bool() const {
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262 assert(Type == Zero || Type == One);
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263 return Type == One;
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264 }
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265
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266 friend raw_ostream &operator<<(raw_ostream &OS, const BitValue &BV);
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267 };
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268
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269 // This operation must be idempotent, i.e. ref(ref(V)) == ref(V).
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270 inline BitTracker::BitValue
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271 BitTracker::BitValue::ref(const BitValue &V) {
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272 if (V.Type != Ref)
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273 return BitValue(V.Type);
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274 if (V.RefI.Reg != 0)
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275 return BitValue(V.RefI.Reg, V.RefI.Pos);
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276 return self();
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277 }
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278
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279 inline BitTracker::BitValue
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280 BitTracker::BitValue::self(const BitRef &Self) {
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281 return BitValue(Self.Reg, Self.Pos);
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282 }
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283
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284 // A sequence of bits starting from index B up to and including index E.
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285 // If E < B, the mask represents two sections: [0..E] and [B..W) where
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286 // W is the width of the register.
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287 struct BitTracker::BitMask {
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288 BitMask() = default;
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289 BitMask(uint16_t b, uint16_t e) : B(b), E(e) {}
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290
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291 uint16_t first() const { return B; }
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292 uint16_t last() const { return E; }
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293
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294 private:
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295 uint16_t B = 0;
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296 uint16_t E = 0;
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297 };
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298
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299 // Representation of a register: a list of BitValues.
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300 struct BitTracker::RegisterCell {
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301 RegisterCell(uint16_t Width = DefaultBitN) : Bits(Width) {}
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302
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303 uint16_t width() const {
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304 return Bits.size();
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305 }
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306
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307 const BitValue &operator[](uint16_t BitN) const {
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308 assert(BitN < Bits.size());
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309 return Bits[BitN];
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310 }
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311 BitValue &operator[](uint16_t BitN) {
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312 assert(BitN < Bits.size());
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313 return Bits[BitN];
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314 }
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315
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316 bool meet(const RegisterCell &RC, Register SelfR);
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317 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
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318 RegisterCell extract(const BitMask &M) const; // Returns a new cell.
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319 RegisterCell &rol(uint16_t Sh); // Rotate left.
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320 RegisterCell &fill(uint16_t B, uint16_t E, const BitValue &V);
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321 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
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322 uint16_t cl(bool B) const;
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323 uint16_t ct(bool B) const;
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324
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325 bool operator== (const RegisterCell &RC) const;
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326 bool operator!= (const RegisterCell &RC) const {
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327 return !operator==(RC);
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328 }
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329
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330 // Replace the ref-to-reg-0 bit values with the given register.
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331 RegisterCell ®ify(unsigned R);
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332
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333 // Generate a "ref" cell for the corresponding register. In the resulting
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334 // cell each bit will be described as being the same as the corresponding
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335 // bit in register Reg (i.e. the cell is "defined" by register Reg).
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336 static RegisterCell self(unsigned Reg, uint16_t Width);
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337 // Generate a "top" cell of given size.
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338 static RegisterCell top(uint16_t Width);
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339 // Generate a cell that is a "ref" to another cell.
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340 static RegisterCell ref(const RegisterCell &C);
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341
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342 private:
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343 // The DefaultBitN is here only to avoid frequent reallocation of the
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344 // memory in the vector.
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345 static const unsigned DefaultBitN = 32;
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346 using BitValueList = SmallVector<BitValue, DefaultBitN>;
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347 BitValueList Bits;
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348
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349 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
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350 };
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351
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352 inline bool BitTracker::has(unsigned Reg) const {
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353 return Map.find(Reg) != Map.end();
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354 }
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355
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356 inline const BitTracker::RegisterCell&
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357 BitTracker::lookup(unsigned Reg) const {
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358 CellMapType::const_iterator F = Map.find(Reg);
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359 assert(F != Map.end());
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360 return F->second;
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361 }
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362
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363 inline BitTracker::RegisterCell
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364 BitTracker::RegisterCell::self(unsigned Reg, uint16_t Width) {
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365 RegisterCell RC(Width);
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366 for (uint16_t i = 0; i < Width; ++i)
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367 RC.Bits[i] = BitValue::self(BitRef(Reg, i));
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368 return RC;
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369 }
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370
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371 inline BitTracker::RegisterCell
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372 BitTracker::RegisterCell::top(uint16_t Width) {
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373 RegisterCell RC(Width);
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374 for (uint16_t i = 0; i < Width; ++i)
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375 RC.Bits[i] = BitValue(BitValue::Top);
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376 return RC;
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377 }
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378
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379 inline BitTracker::RegisterCell
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380 BitTracker::RegisterCell::ref(const RegisterCell &C) {
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381 uint16_t W = C.width();
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382 RegisterCell RC(W);
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383 for (unsigned i = 0; i < W; ++i)
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384 RC[i] = BitValue::ref(C[i]);
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385 return RC;
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386 }
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387
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388 // A class to evaluate target's instructions and update the cell maps.
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389 // This is used internally by the bit tracker. A target that wants to
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390 // utilize this should implement the evaluation functions (noted below)
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391 // in a subclass of this class.
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392 struct BitTracker::MachineEvaluator {
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393 MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
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394 : TRI(T), MRI(M) {}
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395 virtual ~MachineEvaluator() = default;
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396
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397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
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398
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399 RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
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400 void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
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401
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402 // A result of any operation should use refs to the source cells, not
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403 // the cells directly. This function is a convenience wrapper to quickly
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404 // generate a ref for a cell corresponding to a register reference.
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405 RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const {
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406 RegisterCell RC = getCell(RR, M);
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407 return RegisterCell::ref(RC);
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408 }
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409
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410 // Helper functions.
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411 // Check if a cell is an immediate value (i.e. all bits are either 0 or 1).
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412 bool isInt(const RegisterCell &A) const;
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413 // Convert cell to an immediate value.
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414 uint64_t toInt(const RegisterCell &A) const;
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415
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416 // Generate cell from an immediate value.
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417 RegisterCell eIMM(int64_t V, uint16_t W) const;
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418 RegisterCell eIMM(const ConstantInt *CI) const;
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419
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420 // Arithmetic.
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421 RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const;
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422 RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const;
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423 RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const;
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424 RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const;
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425
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426 // Shifts.
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427 RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const;
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428 RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const;
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429 RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const;
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430
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431 // Logical.
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432 RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const;
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433 RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const;
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434 RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const;
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435 RegisterCell eNOT(const RegisterCell &A1) const;
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436
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437 // Set bit, clear bit.
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438 RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const;
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439 RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const;
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440
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441 // Count leading/trailing bits (zeros/ones).
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442 RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const;
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443 RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const;
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444
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445 // Sign/zero extension.
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446 RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const;
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447 RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const;
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448
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449 // Extract/insert
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450 // XTR R,b,e: extract bits from A1 starting at bit b, ending at e-1.
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451 // INS R,S,b: take R and replace bits starting from b with S.
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452 RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const;
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453 RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2,
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454 uint16_t AtN) const;
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455
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456 // User-provided functions for individual targets:
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457
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458 // Return a sub-register mask that indicates which bits in Reg belong
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459 // to the subregister Sub. These bits are assumed to be contiguous in
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460 // the super-register, and have the same ordering in the sub-register
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461 // as in the super-register. It is valid to call this function with
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462 // Sub == 0, in this case, the function should return a mask that spans
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463 // the entire register Reg (which is what the default implementation
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464 // does).
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207
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465 virtual BitMask mask(Register Reg, unsigned Sub) const;
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150
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466 // Indicate whether a given register class should be tracked.
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467 virtual bool track(const TargetRegisterClass *RC) const { return true; }
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468 // Evaluate a non-branching machine instruction, given the cell map with
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469 // the input values. Place the results in the Outputs map. Return "true"
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470 // if evaluation succeeded, "false" otherwise.
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471 virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
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472 CellMapType &Outputs) const;
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473 // Evaluate a branch, given the cell map with the input values. Fill out
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474 // a list of all possible branch targets and indicate (through a flag)
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475 // whether the branch could fall-through. Return "true" if this information
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476 // has been successfully computed, "false" otherwise.
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477 virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
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478 BranchTargetList &Targets, bool &FallsThru) const = 0;
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479 // Given a register class RC, return a register class that should be assumed
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480 // when a register from class RC is used with a subregister of index Idx.
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481 virtual const TargetRegisterClass&
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482 composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const {
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483 if (Idx == 0)
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484 return RC;
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485 llvm_unreachable("Unimplemented composeWithSubRegIndex");
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486 }
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487 // Return the size in bits of the physical register Reg.
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207
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488 virtual uint16_t getPhysRegBitWidth(MCRegister Reg) const;
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150
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489
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490 const TargetRegisterInfo &TRI;
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491 MachineRegisterInfo &MRI;
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492 };
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493
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494 } // end namespace llvm
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495
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496 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
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