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221
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX9 %s
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3 ; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
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4 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX10 %s
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5 ; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
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236
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6 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX11 %s
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7 ; RUN: FileCheck --enable-var-scope --check-prefixes=DBG,DBG11 %s < %t
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150
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8 ; REQUIRES: asserts
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9
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221
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10 ; FIXME: Verifier error with xnack enabled.
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11
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12 ; DBG-LABEL: cluster_load_cluster_store:
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13
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236
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14 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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221
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15 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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16 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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17 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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18 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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19
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150
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20 ; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
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21 ; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
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22 ; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
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221
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23
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236
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24 ; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
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25 ; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
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26 ; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
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27
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221
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28 ; DBG-NOT: Cluster ld/st
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29
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252
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30 define amdgpu_kernel void @cluster_load_cluster_store(ptr noalias %lb, ptr noalias %sb) {
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221
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31 ; GFX9-LABEL: cluster_load_cluster_store:
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32 ; GFX9: ; %bb.0: ; %bb
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236
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33 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
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34 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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236
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35 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
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36 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
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221
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37 ; GFX9-NEXT: flat_load_dword v2, v[0:1]
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38 ; GFX9-NEXT: flat_load_dword v3, v[0:1] offset:8
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39 ; GFX9-NEXT: flat_load_dword v4, v[0:1] offset:16
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40 ; GFX9-NEXT: flat_load_dword v5, v[0:1] offset:24
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236
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41 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
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42 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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221
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43 ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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44 ; GFX9-NEXT: flat_store_dword v[0:1], v2
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45 ; GFX9-NEXT: flat_store_dword v[0:1], v3 offset:8
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46 ; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:16
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47 ; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:24
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48 ; GFX9-NEXT: s_endpgm
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49 ;
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50 ; GFX10-LABEL: cluster_load_cluster_store:
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51 ; GFX10: ; %bb.0: ; %bb
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236
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52 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
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53 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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236
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54 ; GFX10-NEXT: s_add_u32 s4, s0, 8
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55 ; GFX10-NEXT: s_addc_u32 s5, s1, 0
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56 ; GFX10-NEXT: s_add_u32 s6, s0, 16
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57 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
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58 ; GFX10-NEXT: s_addc_u32 s7, s1, 0
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59 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
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60 ; GFX10-NEXT: s_add_u32 s0, s0, 24
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61 ; GFX10-NEXT: v_mov_b32_e32 v2, s4
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62 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
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63 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
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221
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64 ; GFX10-NEXT: v_mov_b32_e32 v4, s6
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236
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65 ; GFX10-NEXT: v_mov_b32_e32 v5, s7
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221
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66 ; GFX10-NEXT: v_mov_b32_e32 v7, s1
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67 ; GFX10-NEXT: v_mov_b32_e32 v6, s0
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68 ; GFX10-NEXT: s_clause 0x3
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69 ; GFX10-NEXT: flat_load_dword v8, v[0:1]
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70 ; GFX10-NEXT: flat_load_dword v9, v[2:3]
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71 ; GFX10-NEXT: flat_load_dword v10, v[4:5]
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72 ; GFX10-NEXT: flat_load_dword v11, v[6:7]
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236
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73 ; GFX10-NEXT: s_add_u32 s0, s2, 8
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74 ; GFX10-NEXT: s_addc_u32 s1, s3, 0
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75 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
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221
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76 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
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77 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
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236
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78 ; GFX10-NEXT: s_add_u32 s0, s2, 16
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79 ; GFX10-NEXT: s_addc_u32 s1, s3, 0
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80 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
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81 ; GFX10-NEXT: s_add_u32 s2, s2, 24
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82 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
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221
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83 ; GFX10-NEXT: v_mov_b32_e32 v5, s1
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236
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84 ; GFX10-NEXT: v_mov_b32_e32 v4, s0
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221
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85 ; GFX10-NEXT: v_mov_b32_e32 v7, s3
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86 ; GFX10-NEXT: v_mov_b32_e32 v6, s2
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87 ; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
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88 ; GFX10-NEXT: flat_store_dword v[0:1], v8
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89 ; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(3)
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90 ; GFX10-NEXT: flat_store_dword v[2:3], v9
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91 ; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)
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92 ; GFX10-NEXT: flat_store_dword v[4:5], v10
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93 ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)
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94 ; GFX10-NEXT: flat_store_dword v[6:7], v11
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95 ; GFX10-NEXT: s_endpgm
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236
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96 ;
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97 ; GFX11-LABEL: cluster_load_cluster_store:
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98 ; GFX11: ; %bb.0: ; %bb
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99 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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100 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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101 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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102 ; GFX11-NEXT: s_clause 0x3
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103 ; GFX11-NEXT: flat_load_b32 v2, v[0:1]
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104 ; GFX11-NEXT: flat_load_b32 v3, v[0:1] offset:8
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105 ; GFX11-NEXT: flat_load_b32 v4, v[0:1] offset:16
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106 ; GFX11-NEXT: flat_load_b32 v5, v[0:1] offset:24
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107 ; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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108 ; GFX11-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
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109 ; GFX11-NEXT: flat_store_b32 v[0:1], v2
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110 ; GFX11-NEXT: s_waitcnt vmcnt(2) lgkmcnt(3)
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111 ; GFX11-NEXT: flat_store_b32 v[0:1], v3 offset:8
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112 ; GFX11-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)
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113 ; GFX11-NEXT: flat_store_b32 v[0:1], v4 offset:16
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114 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)
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115 ; GFX11-NEXT: flat_store_b32 v[0:1], v5 offset:24
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116 ; GFX11-NEXT: s_endpgm
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221
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117 bb:
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252
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118 %ld0 = load i32, ptr %lb
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119 %la1 = getelementptr inbounds i32, ptr %lb, i32 2
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120 %ld1 = load i32, ptr %la1
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121 %la2 = getelementptr inbounds i32, ptr %lb, i32 4
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122 %ld2 = load i32, ptr %la2
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123 %la3 = getelementptr inbounds i32, ptr %lb, i32 6
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124 %ld3 = load i32, ptr %la3
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150
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125
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252
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126 store i32 %ld0, ptr %sb
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127 %sa1 = getelementptr inbounds i32, ptr %sb, i32 2
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128 store i32 %ld1, ptr %sa1
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129 %sa2 = getelementptr inbounds i32, ptr %sb, i32 4
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130 store i32 %ld2, ptr %sa2
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131 %sa3 = getelementptr inbounds i32, ptr %sb, i32 6
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132 store i32 %ld3, ptr %sa3
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150
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133
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134 ret void
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135 }
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136
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221
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137 ; DBG-LABEL: cluster_load_valu_cluster_store:
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138
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236
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139 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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221
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140 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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141 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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142 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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143 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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144
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150
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145 ; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
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146 ; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
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147 ; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
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221
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148
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236
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149 ; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
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150 ; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
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151 ; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
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152
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221
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153 ; DBG-NOT: Cluster ld/st
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154
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252
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155 define amdgpu_kernel void @cluster_load_valu_cluster_store(ptr noalias %lb, ptr noalias %sb) {
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221
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156 ; GFX9-LABEL: cluster_load_valu_cluster_store:
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157 ; GFX9: ; %bb.0: ; %bb
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236
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158 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
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159 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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236
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160 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
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161 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
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221
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162 ; GFX9-NEXT: flat_load_dword v2, v[0:1]
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163 ; GFX9-NEXT: flat_load_dword v3, v[0:1] offset:8
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164 ; GFX9-NEXT: flat_load_dword v4, v[0:1] offset:16
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165 ; GFX9-NEXT: flat_load_dword v5, v[0:1] offset:24
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236
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166 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
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167 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
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221
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168 ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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169 ; GFX9-NEXT: flat_store_dword v[0:1], v2
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170 ; GFX9-NEXT: v_add_u32_e32 v2, 1, v3
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171 ; GFX9-NEXT: flat_store_dword v[0:1], v4 offset:16
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172 ; GFX9-NEXT: flat_store_dword v[0:1], v2 offset:8
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173 ; GFX9-NEXT: flat_store_dword v[0:1], v5 offset:24
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174 ; GFX9-NEXT: s_endpgm
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175 ;
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176 ; GFX10-LABEL: cluster_load_valu_cluster_store:
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177 ; GFX10: ; %bb.0: ; %bb
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236
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178 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
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179 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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236
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180 ; GFX10-NEXT: s_add_u32 s4, s0, 8
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181 ; GFX10-NEXT: s_addc_u32 s5, s1, 0
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182 ; GFX10-NEXT: v_mov_b32_e32 v2, s4
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183 ; GFX10-NEXT: s_add_u32 s6, s0, 16
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184 ; GFX10-NEXT: v_mov_b32_e32 v3, s5
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185 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
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186 ; GFX10-NEXT: s_addc_u32 s7, s1, 0
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187 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
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188 ; GFX10-NEXT: s_add_u32 s0, s0, 24
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189 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
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190 ; GFX10-NEXT: v_mov_b32_e32 v4, s6
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191 ; GFX10-NEXT: v_mov_b32_e32 v5, s7
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192 ; GFX10-NEXT: flat_load_dword v6, v[2:3]
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221
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193 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
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194 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
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195 ; GFX10-NEXT: s_clause 0x2
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196 ; GFX10-NEXT: flat_load_dword v8, v[0:1]
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197 ; GFX10-NEXT: flat_load_dword v9, v[4:5]
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198 ; GFX10-NEXT: flat_load_dword v10, v[2:3]
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236
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199 ; GFX10-NEXT: s_add_u32 s0, s2, 8
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200 ; GFX10-NEXT: s_addc_u32 s1, s3, 0
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201 ; GFX10-NEXT: s_add_u32 s4, s2, 16
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221
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202 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
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236
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203 ; GFX10-NEXT: s_addc_u32 s5, s3, 0
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204 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
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221
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205 ; GFX10-NEXT: v_mov_b32_e32 v2, s0
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236
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206 ; GFX10-NEXT: s_add_u32 s0, s2, 24
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207 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
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208 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
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209 ; GFX10-NEXT: s_addc_u32 s1, s3, 0
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210 ; GFX10-NEXT: v_mov_b32_e32 v5, s5
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221
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211 ; GFX10-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
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212 ; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v6
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213 ; GFX10-NEXT: v_mov_b32_e32 v7, s1
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214 ; GFX10-NEXT: v_mov_b32_e32 v6, s0
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215 ; GFX10-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
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216 ; GFX10-NEXT: flat_store_dword v[0:1], v8
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217 ; GFX10-NEXT: s_waitcnt vmcnt(1) lgkmcnt(2)
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218 ; GFX10-NEXT: flat_store_dword v[4:5], v9
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219 ; GFX10-NEXT: flat_store_dword v[2:3], v11
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220 ; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)
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221 ; GFX10-NEXT: flat_store_dword v[6:7], v10
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222 ; GFX10-NEXT: s_endpgm
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236
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223 ;
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224 ; GFX11-LABEL: cluster_load_valu_cluster_store:
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225 ; GFX11: ; %bb.0: ; %bb
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226 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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227 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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228 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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229 ; GFX11-NEXT: s_clause 0x3
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230 ; GFX11-NEXT: flat_load_b32 v2, v[0:1] offset:8
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231 ; GFX11-NEXT: flat_load_b32 v3, v[0:1]
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232 ; GFX11-NEXT: flat_load_b32 v4, v[0:1] offset:16
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233 ; GFX11-NEXT: flat_load_b32 v5, v[0:1] offset:24
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234 ; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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235 ; GFX11-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
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236 ; GFX11-NEXT: v_add_nc_u32_e32 v2, 1, v2
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237 ; GFX11-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
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238 ; GFX11-NEXT: s_clause 0x1
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239 ; GFX11-NEXT: flat_store_b32 v[0:1], v3
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240 ; GFX11-NEXT: flat_store_b32 v[0:1], v2 offset:8
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241 ; GFX11-NEXT: s_waitcnt vmcnt(1) lgkmcnt(3)
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242 ; GFX11-NEXT: flat_store_b32 v[0:1], v4 offset:16
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243 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(3)
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244 ; GFX11-NEXT: flat_store_b32 v[0:1], v5 offset:24
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245 ; GFX11-NEXT: s_endpgm
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221
|
246 bb:
|
|
252
|
247 %ld0 = load i32, ptr %lb
|
|
|
248 %la1 = getelementptr inbounds i32, ptr %lb, i32 2
|
|
|
249 %ld1 = load i32, ptr %la1
|
|
|
250 %la2 = getelementptr inbounds i32, ptr %lb, i32 4
|
|
|
251 %ld2 = load i32, ptr %la2
|
|
|
252 %la3 = getelementptr inbounds i32, ptr %lb, i32 6
|
|
|
253 %ld3 = load i32, ptr %la3
|
|
150
|
254
|
|
252
|
255 store i32 %ld0, ptr %sb
|
|
|
256 %sa1 = getelementptr inbounds i32, ptr %sb, i32 2
|
|
150
|
257 %add = add i32 %ld1, 1
|
|
252
|
258 store i32 %add, ptr %sa1
|
|
|
259 %sa2 = getelementptr inbounds i32, ptr %sb, i32 4
|
|
|
260 store i32 %ld2, ptr %sa2
|
|
|
261 %sa3 = getelementptr inbounds i32, ptr %sb, i32 6
|
|
|
262 store i32 %ld3, ptr %sa3
|
|
150
|
263
|
|
|
264 ret void
|
|
|
265 }
|
|
221
|
266
|
|
|
267 ; Cluster loads from the same texture with different coordinates
|
|
|
268 ; DBG-LABEL: cluster_image_load:
|
|
|
269 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
|
|
|
270 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
|
|
|
271 ; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
|
|
|
272 ; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD
|
|
|
273 ; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD
|
|
|
274 define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) {
|
|
|
275 ; GFX9-LABEL: cluster_image_load:
|
|
|
276 ; GFX9: ; %bb.0: ; %entry
|
|
|
277 ; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
|
|
|
278 ; GFX9-NEXT: v_add_u32_e32 v3, 1, v1
|
|
|
279 ; GFX9-NEXT: v_add_u32_e32 v6, 2, v0
|
|
|
280 ; GFX9-NEXT: v_add_u32_e32 v7, 2, v1
|
|
|
281 ; GFX9-NEXT: image_load v[2:5], v[2:3], s[0:7] dmask:0xf unorm
|
|
|
282 ; GFX9-NEXT: image_load v[6:9], v[6:7], s[0:7] dmask:0xf unorm
|
|
|
283 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
|
284 ; GFX9-NEXT: v_add_f32_e32 v5, v5, v9
|
|
|
285 ; GFX9-NEXT: v_add_f32_e32 v4, v4, v8
|
|
|
286 ; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
|
|
|
287 ; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
|
|
|
288 ; GFX9-NEXT: image_store v[2:5], v[0:1], s[8:15] dmask:0xf unorm
|
|
|
289 ; GFX9-NEXT: s_endpgm
|
|
|
290 ;
|
|
|
291 ; GFX10-LABEL: cluster_image_load:
|
|
|
292 ; GFX10: ; %bb.0: ; %entry
|
|
|
293 ; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v0
|
|
|
294 ; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v1
|
|
|
295 ; GFX10-NEXT: v_add_nc_u32_e32 v12, 2, v0
|
|
|
296 ; GFX10-NEXT: v_add_nc_u32_e32 v13, 2, v1
|
|
|
297 ; GFX10-NEXT: s_clause 0x1
|
|
|
298 ; GFX10-NEXT: image_load v[2:5], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
299 ; GFX10-NEXT: image_load v[6:9], v[12:13], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
300 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
301 ; GFX10-NEXT: v_add_f32_e32 v5, v5, v9
|
|
|
302 ; GFX10-NEXT: v_add_f32_e32 v4, v4, v8
|
|
|
303 ; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
|
|
|
304 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v6
|
|
|
305 ; GFX10-NEXT: image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
306 ; GFX10-NEXT: s_endpgm
|
|
236
|
307 ;
|
|
|
308 ; GFX11-LABEL: cluster_image_load:
|
|
|
309 ; GFX11: ; %bb.0: ; %entry
|
|
|
310 ; GFX11-NEXT: v_add_nc_u32_e32 v2, 1, v0
|
|
|
311 ; GFX11-NEXT: v_add_nc_u32_e32 v3, 1, v1
|
|
|
312 ; GFX11-NEXT: v_add_nc_u32_e32 v6, 2, v0
|
|
|
313 ; GFX11-NEXT: v_add_nc_u32_e32 v7, 2, v1
|
|
|
314 ; GFX11-NEXT: s_clause 0x1
|
|
|
315 ; GFX11-NEXT: image_load v[2:5], v[2:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
316 ; GFX11-NEXT: image_load v[6:9], v[6:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
317 ; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
|
318 ; GFX11-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v5, v5, v9
|
|
|
319 ; GFX11-NEXT: v_dual_add_f32 v4, v4, v8 :: v_dual_add_f32 v3, v3, v7
|
|
|
320 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
252
|
321 ; GFX11-NEXT: s_nop 0
|
|
236
|
322 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
|
323 ; GFX11-NEXT: s_endpgm
|
|
221
|
324 entry:
|
|
|
325 %x1 = add i32 %x, 1
|
|
|
326 %y1 = add i32 %y, 1
|
|
236
|
327 %val1 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, <8 x i32> %src, i32 0, i32 0)
|
|
221
|
328 %x2 = add i32 %x, 2
|
|
|
329 %y2 = add i32 %y, 2
|
|
236
|
330 %val2 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, <8 x i32> %src, i32 0, i32 0)
|
|
221
|
331 %val = fadd fast <4 x float> %val1, %val2
|
|
|
332 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
|
|
|
333 ret void
|
|
|
334 }
|
|
|
335
|
|
|
336 ; Don't cluster loads from different textures
|
|
|
337 ; DBG-LABEL: no_cluster_image_load:
|
|
|
338 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
|
|
|
339 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
|
|
|
340 ; DBG-NOT: {{^}}Cluster ld/st
|
|
|
341 define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) {
|
|
|
342 ; GFX9-LABEL: no_cluster_image_load:
|
|
|
343 ; GFX9: ; %bb.0: ; %entry
|
|
236
|
344 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
|
345 ; GFX9-NEXT: image_load_mip v[3:6], v[0:2], s[0:7] dmask:0xf unorm
|
|
|
346 ; GFX9-NEXT: image_load_mip v[7:10], v[0:2], s[8:15] dmask:0xf unorm
|
|
221
|
347 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
236
|
348 ; GFX9-NEXT: v_add_f32_e32 v6, v6, v10
|
|
221
|
349 ; GFX9-NEXT: v_add_f32_e32 v5, v5, v9
|
|
|
350 ; GFX9-NEXT: v_add_f32_e32 v4, v4, v8
|
|
|
351 ; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
|
|
236
|
352 ; GFX9-NEXT: image_store v[3:6], v[0:1], s[16:23] dmask:0xf unorm
|
|
221
|
353 ; GFX9-NEXT: s_endpgm
|
|
|
354 ;
|
|
|
355 ; GFX10-LABEL: no_cluster_image_load:
|
|
|
356 ; GFX10: ; %bb.0: ; %entry
|
|
236
|
357 ; GFX10-NEXT: v_mov_b32_e32 v10, 0
|
|
|
358 ; GFX10-NEXT: image_load_mip v[2:5], [v0, v1, v10], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
359 ; GFX10-NEXT: image_load_mip v[6:9], [v0, v1, v10], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
221
|
360 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
361 ; GFX10-NEXT: v_add_f32_e32 v5, v5, v9
|
|
|
362 ; GFX10-NEXT: v_add_f32_e32 v4, v4, v8
|
|
|
363 ; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
|
|
|
364 ; GFX10-NEXT: v_add_f32_e32 v2, v2, v6
|
|
|
365 ; GFX10-NEXT: image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
366 ; GFX10-NEXT: s_endpgm
|
|
236
|
367 ;
|
|
|
368 ; GFX11-LABEL: no_cluster_image_load:
|
|
|
369 ; GFX11: ; %bb.0: ; %entry
|
|
|
370 ; GFX11-NEXT: v_mov_b32_e32 v6, 0
|
|
|
371 ; GFX11-NEXT: image_load_mip v[2:5], [v0, v1, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
372 ; GFX11-NEXT: image_load_mip v[6:9], [v0, v1, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
373 ; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
|
374 ; GFX11-NEXT: v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v8
|
|
|
375 ; GFX11-NEXT: v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v2, v2, v6
|
|
|
376 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
252
|
377 ; GFX11-NEXT: s_nop 0
|
|
236
|
378 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
|
379 ; GFX11-NEXT: s_endpgm
|
|
221
|
380 entry:
|
|
|
381 %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0)
|
|
|
382 %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0)
|
|
|
383 %val = fadd fast <4 x float> %val1, %val2
|
|
|
384 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
|
|
|
385 ret void
|
|
|
386 }
|
|
|
387
|
|
|
388 ; Cluster loads from the same texture and sampler with different coordinates
|
|
|
389 ; DBG-LABEL: cluster_image_sample:
|
|
|
390 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
|
|
|
391 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
|
|
|
392 ; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
|
|
|
393 ; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE
|
|
|
394 ; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE
|
|
|
395 define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) {
|
|
|
396 ; GFX9-LABEL: cluster_image_sample:
|
|
|
397 ; GFX9: ; %bb.0: ; %entry
|
|
|
398 ; GFX9-NEXT: v_cvt_f32_i32_e32 v8, v0
|
|
|
399 ; GFX9-NEXT: v_cvt_f32_i32_e32 v9, v1
|
|
|
400 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
|
|
236
|
401 ; GFX9-NEXT: v_mov_b32_e32 v5, v4
|
|
221
|
402 ; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v8
|
|
|
403 ; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v9
|
|
|
404 ; GFX9-NEXT: v_mov_b32_e32 v6, v4
|
|
|
405 ; GFX9-NEXT: v_mov_b32_e32 v7, v4
|
|
|
406 ; GFX9-NEXT: v_add_f32_e32 v8, 2.0, v8
|
|
|
407 ; GFX9-NEXT: v_add_f32_e32 v9, 2.0, v9
|
|
236
|
408 ; GFX9-NEXT: v_mov_b32_e32 v10, 1.0
|
|
221
|
409 ; GFX9-NEXT: v_mov_b32_e32 v11, v10
|
|
|
410 ; GFX9-NEXT: v_mov_b32_e32 v12, v10
|
|
|
411 ; GFX9-NEXT: v_mov_b32_e32 v13, v10
|
|
236
|
412 ; GFX9-NEXT: image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf
|
|
|
413 ; GFX9-NEXT: image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf
|
|
221
|
414 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
|
415 ; GFX9-NEXT: v_add_f32_e32 v5, v5, v9
|
|
|
416 ; GFX9-NEXT: v_add_f32_e32 v4, v4, v8
|
|
|
417 ; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
|
|
|
418 ; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
|
|
|
419 ; GFX9-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm
|
|
|
420 ; GFX9-NEXT: s_endpgm
|
|
|
421 ;
|
|
|
422 ; GFX10-LABEL: cluster_image_sample:
|
|
|
423 ; GFX10: ; %bb.0: ; %entry
|
|
236
|
424 ; GFX10-NEXT: v_cvt_f32_i32_e32 v8, v0
|
|
|
425 ; GFX10-NEXT: v_cvt_f32_i32_e32 v9, v1
|
|
|
426 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
|
|
221
|
427 ; GFX10-NEXT: v_mov_b32_e32 v10, 1.0
|
|
236
|
428 ; GFX10-NEXT: v_add_f32_e32 v2, 1.0, v8
|
|
|
429 ; GFX10-NEXT: v_add_f32_e32 v3, 1.0, v9
|
|
|
430 ; GFX10-NEXT: v_mov_b32_e32 v5, v4
|
|
|
431 ; GFX10-NEXT: v_mov_b32_e32 v6, v4
|
|
|
432 ; GFX10-NEXT: v_mov_b32_e32 v7, v4
|
|
|
433 ; GFX10-NEXT: v_add_f32_e32 v8, 2.0, v8
|
|
|
434 ; GFX10-NEXT: v_add_f32_e32 v9, 2.0, v9
|
|
|
435 ; GFX10-NEXT: v_mov_b32_e32 v11, v10
|
|
|
436 ; GFX10-NEXT: v_mov_b32_e32 v12, v10
|
|
|
437 ; GFX10-NEXT: v_mov_b32_e32 v13, v10
|
|
|
438 ; GFX10-NEXT: s_clause 0x1
|
|
|
439 ; GFX10-NEXT: image_sample_d v[14:17], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
440 ; GFX10-NEXT: image_sample_d v[18:21], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
221
|
441 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
236
|
442 ; GFX10-NEXT: v_add_f32_e32 v5, v17, v21
|
|
|
443 ; GFX10-NEXT: v_add_f32_e32 v4, v16, v20
|
|
|
444 ; GFX10-NEXT: v_add_f32_e32 v3, v15, v19
|
|
|
445 ; GFX10-NEXT: v_add_f32_e32 v2, v14, v18
|
|
221
|
446 ; GFX10-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
|
447 ; GFX10-NEXT: s_endpgm
|
|
236
|
448 ;
|
|
|
449 ; GFX11-LABEL: cluster_image_sample:
|
|
|
450 ; GFX11: ; %bb.0: ; %entry
|
|
252
|
451 ; GFX11-NEXT: v_cvt_f32_i32_e32 v4, v0
|
|
|
452 ; GFX11-NEXT: v_cvt_f32_i32_e32 v5, v1
|
|
|
453 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
|
454 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
|
455 ; GFX11-NEXT: v_dual_mov_b32 v6, 1.0 :: v_dual_add_f32 v11, 2.0, v5
|
|
|
456 ; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v5 :: v_dual_add_f32 v8, 1.0, v4
|
|
|
457 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
|
458 ; GFX11-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_add_f32 v10, 2.0, v4
|
|
|
459 ; GFX11-NEXT: v_mov_b32_e32 v7, v6
|
|
236
|
460 ; GFX11-NEXT: s_clause 0x1
|
|
252
|
461 ; GFX11-NEXT: image_sample_d v[2:5], [v8, v9, v2, v2, v[2:3]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
|
462 ; GFX11-NEXT: image_sample_d v[6:9], [v10, v11, v6, v6, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
236
|
463 ; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
252
|
464 ; GFX11-NEXT: v_dual_add_f32 v5, v5, v9 :: v_dual_add_f32 v4, v4, v8
|
|
236
|
465 ; GFX11-NEXT: v_dual_add_f32 v3, v3, v7 :: v_dual_add_f32 v2, v2, v6
|
|
|
466 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
|
|
252
|
467 ; GFX11-NEXT: s_nop 0
|
|
236
|
468 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
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469 ; GFX11-NEXT: s_endpgm
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221
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470 entry:
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471 %s = sitofp i32 %x to float
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472 %t = sitofp i32 %y to float
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473 %s1 = fadd float %s, 1.0
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474 %t1 = fadd float %t, 1.0
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475 %val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
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476 %s2 = fadd float %s, 2.0
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477 %t2 = fadd float %t, 2.0
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478 %val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
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479 %val = fadd fast <4 x float> %val1, %val2
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480 call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
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481 ret void
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482 }
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483
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236
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484 declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
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221
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485 declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
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486 declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
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487 declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
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