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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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173
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2
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3 ; NOTE: The checks for opt are NOT added by the update script. Those
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4 ; checks are looking for the absence of specific metadata, which
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5 ; cannot be expressed reliably by the generated checks.
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150
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6
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173
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7 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ISA
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8 ; RUN: opt --amdgpu-annotate-uniform -S %s | FileCheck %s -check-prefix=UNIFORM
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9 ; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s | FileCheck %s -check-prefix=CONTROLFLOW
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10
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11 ; This module creates a divergent branch in block Flow2. The branch is
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12 ; marked as divergent by the divergence analysis but the condition is
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13 ; not. This test ensures that the divergence of the branch is tested,
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14 ; not its condition, so that branch is correctly emitted as divergent.
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150
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15
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16 target triple = "amdgcn-mesa-mesa3d"
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17
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173
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18 define amdgpu_ps void @main(i32 %0, float %1) {
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19 ; ISA-LABEL: main:
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20 ; ISA: ; %bb.0: ; %start
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21 ; ISA-NEXT: v_readfirstlane_b32 s0, v0
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22 ; ISA-NEXT: s_mov_b32 m0, s0
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236
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23 ; ISA-NEXT: s_mov_b32 s8, 0
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173
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24 ; ISA-NEXT: v_interp_p1_f32_e32 v0, v1, attr0.x
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25 ; ISA-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0
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236
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26 ; ISA-NEXT: s_mov_b64 s[0:1], 0
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173
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27 ; ISA-NEXT: ; implicit-def: $sgpr4_sgpr5
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236
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28 ; ISA-NEXT: ; implicit-def: $sgpr2_sgpr3
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29 ; ISA-NEXT: s_branch .LBB0_3
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30 ; ISA-NEXT: .LBB0_1: ; %Flow1
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173
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31 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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236
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32 ; ISA-NEXT: s_or_b64 exec, exec, s[6:7]
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33 ; ISA-NEXT: s_mov_b64 s[6:7], 0
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34 ; ISA-NEXT: .LBB0_2: ; %Flow
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173
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35 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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236
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36 ; ISA-NEXT: s_and_b64 s[10:11], exec, s[4:5]
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37 ; ISA-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
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38 ; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
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39 ; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec
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40 ; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
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41 ; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1]
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42 ; ISA-NEXT: s_cbranch_execz .LBB0_6
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43 ; ISA-NEXT: .LBB0_3: ; %loop
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173
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44 ; ISA-NEXT: ; =>This Inner Loop Header: Depth=1
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236
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45 ; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec
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46 ; ISA-NEXT: s_cmp_lt_u32 s8, 32
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47 ; ISA-NEXT: s_mov_b64 s[6:7], -1
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48 ; ISA-NEXT: s_cbranch_scc0 .LBB0_2
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173
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49 ; ISA-NEXT: ; %bb.4: ; %endif1
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50 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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236
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51 ; ISA-NEXT: s_mov_b64 s[4:5], -1
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52 ; ISA-NEXT: s_and_saveexec_b64 s[6:7], vcc
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53 ; ISA-NEXT: s_cbranch_execz .LBB0_1
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173
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54 ; ISA-NEXT: ; %bb.5: ; %endif2
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55 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1
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236
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56 ; ISA-NEXT: s_add_i32 s8, s8, 1
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57 ; ISA-NEXT: s_xor_b64 s[4:5], exec, -1
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58 ; ISA-NEXT: s_branch .LBB0_1
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59 ; ISA-NEXT: .LBB0_6: ; %Flow2
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60 ; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
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173
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61 ; ISA-NEXT: v_mov_b32_e32 v1, 0
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236
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62 ; ISA-NEXT: s_and_saveexec_b64 s[0:1], s[2:3]
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173
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63 ; ISA-NEXT: ; %bb.7: ; %if1
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64 ; ISA-NEXT: v_sqrt_f32_e32 v1, v0
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65 ; ISA-NEXT: ; %bb.8: ; %endloop
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66 ; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
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67 ; ISA-NEXT: exp mrt0 v1, v1, v1, v1 done vm
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68 ; ISA-NEXT: s_endpgm
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150
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69 start:
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70 %v0 = call float @llvm.amdgcn.interp.p1(float %1, i32 0, i32 0, i32 %0)
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71 br label %loop
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72
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173
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73 loop: ; preds = %Flow, %start
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74 %v1 = phi i32 [ 0, %start ], [ %6, %Flow ]
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150
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75 %v2 = icmp ugt i32 %v1, 31
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173
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76 %2 = xor i1 %v2, true
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77 br i1 %2, label %endif1, label %Flow
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78
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79 Flow1: ; preds = %endif2, %endif1
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80 %3 = phi i32 [ %v5, %endif2 ], [ undef, %endif1 ]
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81 %4 = phi i1 [ false, %endif2 ], [ true, %endif1 ]
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82 br label %Flow
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150
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83
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173
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84 ; UNIFORM-LABEL: Flow2:
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85 ; UNIFORM-NEXT: br i1 %8, label %if1, label %endloop
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86 ; UNIFORM-NOT: !amdgpu.uniform
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87 ; UNIFORM: if1:
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88
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89 ; CONTROLFLOW-LABEL: Flow2:
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90 ; CONTROLFLOW-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %{{.*}})
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91 ; CONTROLFLOW-NEXT: [[IF:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %{{.*}})
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92 ; CONTROLFLOW-NEXT: [[COND:%.*]] = extractvalue { i1, i64 } [[IF]], 0
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93 ; CONTROLFLOW-NEXT: %{{.*}} = extractvalue { i1, i64 } [[IF]], 1
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94 ; CONTROLFLOW-NEXT: br i1 [[COND]], label %if1, label %endloop
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95
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96 Flow2: ; preds = %Flow
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97 br i1 %8, label %if1, label %endloop
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98
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99 if1: ; preds = %Flow2
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150
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100 %v3 = call float @llvm.sqrt.f32(float %v0)
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101 br label %endloop
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102
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173
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103 endif1: ; preds = %loop
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150
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104 %v4 = fcmp ogt float %v0, 0.000000e+00
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173
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105 %5 = xor i1 %v4, true
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106 br i1 %5, label %endif2, label %Flow1
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150
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107
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173
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108 Flow: ; preds = %Flow1, %loop
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109 %6 = phi i32 [ %3, %Flow1 ], [ undef, %loop ]
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110 %7 = phi i1 [ %4, %Flow1 ], [ true, %loop ]
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111 %8 = phi i1 [ false, %Flow1 ], [ true, %loop ]
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112 br i1 %7, label %Flow2, label %loop
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113
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114 endif2: ; preds = %endif1
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150
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115 %v5 = add i32 %v1, 1
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173
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116 br label %Flow1
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150
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117
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173
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118 endloop: ; preds = %if1, %Flow2
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119 %v6 = phi float [ 0.000000e+00, %Flow2 ], [ %v3, %if1 ]
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120 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %v6, float %v6, float %v6, float %v6, i1 true, i1 true)
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150
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121 ret void
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122 }
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123
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173
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124 ; Function Attrs: nounwind readnone speculatable willreturn
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125 declare float @llvm.sqrt.f32(float) #0
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126
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127 ; Function Attrs: nounwind readnone speculatable
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128 declare float @llvm.amdgcn.interp.p1(float, i32 immarg, i32 immarg, i32) #1
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150
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129
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173
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130 ; Function Attrs: inaccessiblememonly nounwind writeonly
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131 declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #2
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132
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133 attributes #0 = { nounwind readnone speculatable willreturn }
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134 attributes #1 = { nounwind readnone speculatable }
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135 attributes #2 = { inaccessiblememonly nounwind writeonly }
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