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221
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s
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3 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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4 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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236
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5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
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221
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6
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7 define i32 @s_add_co_select_user() {
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8 ; GFX7-LABEL: s_add_co_select_user:
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9 ; GFX7: ; %bb.0: ; %bb
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10 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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11 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
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12 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0
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13 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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14 ; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6
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15 ; GFX7-NEXT: s_or_b32 s4, s4, s5
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16 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0
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236
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17 ; GFX7-NEXT: s_addc_u32 s7, s6, 0
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18 ; GFX7-NEXT: s_cselect_b64 s[4:5], -1, 0
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19 ; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
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20 ; GFX7-NEXT: s_cselect_b32 s4, s7, 0
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21 ; GFX7-NEXT: s_cmp_gt_u32 s6, 31
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221
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22 ; GFX7-NEXT: v_mov_b32_e32 v1, s4
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236
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23 ; GFX7-NEXT: s_cselect_b64 vcc, -1, 0
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221
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24 ; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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25 ; GFX7-NEXT: s_setpc_b64 s[30:31]
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26 ;
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27 ; GFX9-LABEL: s_add_co_select_user:
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28 ; GFX9: ; %bb.0: ; %bb
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29 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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30 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
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31 ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0
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32 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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33 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6
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34 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
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236
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35 ; GFX9-NEXT: s_addc_u32 s7, s6, 0
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36 ; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0
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37 ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
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38 ; GFX9-NEXT: s_cselect_b32 s4, s7, 0
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39 ; GFX9-NEXT: s_cmp_gt_u32 s6, 31
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221
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40 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
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41 ; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
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42 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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43 ; GFX9-NEXT: s_setpc_b64 s[30:31]
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44 ;
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45 ; GFX10-LABEL: s_add_co_select_user:
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46 ; GFX10: ; %bb.0: ; %bb
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47 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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48 ; GFX10-NEXT: s_mov_b64 s[4:5], 0
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49 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
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50 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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51 ; GFX10-NEXT: v_add_co_u32 v0, s5, s4, s4
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252
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52 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0
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221
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53 ; GFX10-NEXT: s_addc_u32 s5, s4, 0
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236
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54 ; GFX10-NEXT: s_cselect_b32 s6, -1, 0
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55 ; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
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56 ; GFX10-NEXT: s_cselect_b32 s5, s5, 0
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221
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57 ; GFX10-NEXT: s_cmp_gt_u32 s4, 31
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58 ; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
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236
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59 ; GFX10-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
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221
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60 ; GFX10-NEXT: s_setpc_b64 s[30:31]
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236
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61 ;
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62 ; GFX11-LABEL: s_add_co_select_user:
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63 ; GFX11: ; %bb.0: ; %bb
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64 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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65 ; GFX11-NEXT: s_mov_b64 s[0:1], 0
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66 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
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67 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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68 ; GFX11-NEXT: v_add_co_u32 v0, s1, s0, s0
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69 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
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252
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70 ; GFX11-NEXT: s_cmp_lg_u32 s1, 0
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236
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71 ; GFX11-NEXT: s_addc_u32 s1, s0, 0
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72 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
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73 ; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
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74 ; GFX11-NEXT: s_cselect_b32 s1, s1, 0
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75 ; GFX11-NEXT: s_cmp_gt_u32 s0, 31
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76 ; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0
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77 ; GFX11-NEXT: v_cndmask_b32_e32 v0, s1, v0, vcc_lo
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78 ; GFX11-NEXT: s_setpc_b64 s[30:31]
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221
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79 bb:
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252
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80 %i = load volatile i32, ptr addrspace(4) null, align 8
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221
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81 %i1 = add i32 %i, %i
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82 %i2 = icmp ult i32 %i1, %i
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83 %i3 = zext i1 %i2 to i32
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84 %i4 = add nuw nsw i32 %i3, 0
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85 %i5 = add i32 %i4, %i
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86 %i6 = icmp ult i32 %i5, %i4
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87 %i7 = select i1 %i6, i32 %i5, i32 0
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88 %i8 = icmp ugt i32 %i, 31
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89 %i9 = select i1 %i8, i32 %i1, i32 %i7
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90 ret i32 %i9
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91 }
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92
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93 define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
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94 ; GFX7-LABEL: s_add_co_br_user:
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95 ; GFX7: ; %bb.0: ; %bb
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236
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96 ; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
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221
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97 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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236
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98 ; GFX7-NEXT: s_add_i32 s0, s2, s2
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99 ; GFX7-NEXT: s_cmp_lt_u32 s0, s2
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100 ; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
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101 ; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
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102 ; GFX7-NEXT: s_or_b32 s0, s0, s1
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103 ; GFX7-NEXT: s_cmp_lg_u32 s0, 0
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104 ; GFX7-NEXT: s_addc_u32 s0, s2, 0
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221
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105 ; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
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236
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106 ; GFX7-NEXT: s_cbranch_vccnz .LBB1_2
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221
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107 ; GFX7-NEXT: ; %bb.1: ; %bb0
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108 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
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223
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109 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
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221
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110 ; GFX7-NEXT: v_mov_b32_e32 v2, 9
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111 ; GFX7-NEXT: flat_store_dword v[0:1], v2
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112 ; GFX7-NEXT: s_waitcnt vmcnt(0)
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236
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113 ; GFX7-NEXT: .LBB1_2: ; %bb1
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221
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114 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
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223
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115 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
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221
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116 ; GFX7-NEXT: v_mov_b32_e32 v2, 10
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117 ; GFX7-NEXT: flat_store_dword v[0:1], v2
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118 ; GFX7-NEXT: s_waitcnt vmcnt(0)
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119 ; GFX7-NEXT: s_endpgm
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120 ;
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121 ; GFX9-LABEL: s_add_co_br_user:
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122 ; GFX9: ; %bb.0: ; %bb
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236
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123 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0
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221
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124 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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236
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125 ; GFX9-NEXT: s_add_i32 s0, s2, s2
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126 ; GFX9-NEXT: s_cmp_lt_u32 s0, s2
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127 ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
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128 ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
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129 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
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130 ; GFX9-NEXT: s_addc_u32 s0, s2, 0
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221
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131 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
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236
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132 ; GFX9-NEXT: s_cbranch_vccnz .LBB1_2
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221
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133 ; GFX9-NEXT: ; %bb.1: ; %bb0
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134 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
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223
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135 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
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221
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136 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
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137 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
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138 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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236
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139 ; GFX9-NEXT: .LBB1_2: ; %bb1
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221
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140 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
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223
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141 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
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221
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142 ; GFX9-NEXT: v_mov_b32_e32 v2, 10
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143 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
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144 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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145 ; GFX9-NEXT: s_endpgm
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146 ;
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147 ; GFX10-LABEL: s_add_co_br_user:
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148 ; GFX10: ; %bb.0: ; %bb
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149 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0
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150 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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151 ; GFX10-NEXT: s_add_i32 s1, s0, s0
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236
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152 ; GFX10-NEXT: s_cmp_lt_u32 s1, s0
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153 ; GFX10-NEXT: s_cselect_b32 s1, -1, 0
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221
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154 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
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252
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155 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0
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221
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156 ; GFX10-NEXT: s_addc_u32 s0, s0, 0
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157 ; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
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236
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158 ; GFX10-NEXT: s_cbranch_vccnz .LBB1_2
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221
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159 ; GFX10-NEXT: ; %bb.1: ; %bb0
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160 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
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223
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161 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
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221
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162 ; GFX10-NEXT: v_mov_b32_e32 v2, 9
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163 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
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164 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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236
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165 ; GFX10-NEXT: .LBB1_2: ; %bb1
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221
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166 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
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223
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167 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
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221
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168 ; GFX10-NEXT: v_mov_b32_e32 v2, 10
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169 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
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170 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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171 ; GFX10-NEXT: s_endpgm
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236
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172 ;
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173 ; GFX11-LABEL: s_add_co_br_user:
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174 ; GFX11: ; %bb.0: ; %bb
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175 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
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176 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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177 ; GFX11-NEXT: s_add_i32 s1, s0, s0
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178 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
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179 ; GFX11-NEXT: s_cmp_lt_u32 s1, s0
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180 ; GFX11-NEXT: s_cselect_b32 s1, -1, 0
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181 ; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
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252
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182 ; GFX11-NEXT: s_cmp_lg_u32 s1, 0
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236
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183 ; GFX11-NEXT: s_addc_u32 s0, s0, 0
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184 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
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185 ; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
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186 ; GFX11-NEXT: s_cbranch_vccnz .LBB1_2
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187 ; GFX11-NEXT: ; %bb.1: ; %bb0
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188 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
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189 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 9
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190 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off dlc
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191 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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192 ; GFX11-NEXT: .LBB1_2: ; %bb1
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193 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
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194 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 10
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195 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off dlc
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196 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
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252
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197 ; GFX11-NEXT: s_nop 0
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236
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198 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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199 ; GFX11-NEXT: s_endpgm
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221
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200 bb:
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201 %i1 = add i32 %i, %i
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202 %i2 = icmp ult i32 %i1, %i
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203 %i3 = zext i1 %i2 to i32
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204 %i4 = add nuw nsw i32 %i3, 0
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205 %i5 = add i32 %i4, %i
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206 %i6 = icmp ult i32 %i5, %i4
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207 %i7 = select i1 %i6, i32 %i5, i32 0
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208 br i1 %i6, label %bb0, label %bb1
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209
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210 bb0:
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252
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211 store volatile i32 9, ptr addrspace(1) null
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221
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212 br label %bb1
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213
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214 bb1:
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252
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215 store volatile i32 10, ptr addrspace(1) null
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221
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216 ret void
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217 }
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