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150
|
1 # RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
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2 --- |
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3 define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 {
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252
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4 %f16.val0 = load volatile half, ptr addrspace(1) undef
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5 %f16.val1 = load volatile half, ptr addrspace(1) undef
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6 %f32.val = load volatile float, ptr addrspace(1) undef
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|
150
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7 %f16.add0 = fadd half %f16.val0, 0xH3C00
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8 %f32.add = fadd float %f32.val, 1.000000e+00
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252
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9 store volatile half %f16.add0, ptr addrspace(1) undef
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10 store volatile float %f32.add, ptr addrspace(1) undef
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150
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11 ret void
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12 }
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13
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14 define amdgpu_kernel void @add_f32_1.0_multi_f16_use() #0 {
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252
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15 %f16.val0 = load volatile half, ptr addrspace(1) undef
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16 %f16.val1 = load volatile half, ptr addrspace(1) undef
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17 %f32.val = load volatile float, ptr addrspace(1) undef
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|
150
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18 %f16.add0 = fadd half %f16.val0, 0xH3C00
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19 %f32.add = fadd float %f32.val, 1.000000e+00
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252
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20 store volatile half %f16.add0, ptr addrspace(1) undef
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21 store volatile float %f32.add, ptr addrspace(1) undef
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150
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22 ret void
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23 }
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24
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25 define amdgpu_kernel void @add_f32_1.0_one_f32_use_one_f16_use () #0 {
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252
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26 %f16.val0 = load volatile half, ptr addrspace(1) undef
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27 %f16.val1 = load volatile half, ptr addrspace(1) undef
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28 %f32.val = load volatile float, ptr addrspace(1) undef
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|
150
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29 %f16.add0 = fadd half %f16.val0, 0xH3C00
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30 %f32.add = fadd float %f32.val, 1.000000e+00
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252
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31 store volatile half %f16.add0, ptr addrspace(1) undef
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32 store volatile float %f32.add, ptr addrspace(1) undef
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150
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33 ret void
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34 }
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35
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36 define amdgpu_kernel void @add_f32_1.0_one_f32_use_multi_f16_use () #0 {
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252
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37 %f16.val0 = load volatile half, ptr addrspace(1) undef
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38 %f16.val1 = load volatile half, ptr addrspace(1) undef
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39 %f32.val = load volatile float, ptr addrspace(1) undef
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150
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40 %f16.add0 = fadd half %f16.val0, 0xH3C00
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41 %f16.add1 = fadd half %f16.val1, 0xH3C00
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42 %f32.add = fadd float %f32.val, 1.000000e+00
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252
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43 store volatile half %f16.add0, ptr addrspace(1) undef
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44 store volatile half %f16.add1, ptr addrspace(1) undef
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45 store volatile float %f32.add, ptr addrspace(1) undef
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150
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46 ret void
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47 }
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48
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49 define amdgpu_kernel void @add_i32_1_multi_f16_use() #0 {
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252
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50 %f16.val0 = load volatile half, ptr addrspace(1) undef
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51 %f16.val1 = load volatile half, ptr addrspace(1) undef
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150
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52 %f16.add0 = fadd half %f16.val0, 0xH0001
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53 %f16.add1 = fadd half %f16.val1, 0xH0001
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252
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54 store volatile half %f16.add0, ptr addrspace(1) undef
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55 store volatile half %f16.add1,ptr addrspace(1) undef
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150
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56 ret void
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57 }
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58
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59 define amdgpu_kernel void @add_i32_m2_one_f32_use_multi_f16_use () #0 {
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252
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60 %f16.val0 = load volatile half, ptr addrspace(1) undef
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61 %f16.val1 = load volatile half, ptr addrspace(1) undef
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62 %f32.val = load volatile float, ptr addrspace(1) undef
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|
150
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63 %f16.add0 = fadd half %f16.val0, 0xHFFFE
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64 %f16.add1 = fadd half %f16.val1, 0xHFFFE
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65 %f32.add = fadd float %f32.val, 0xffffffffc0000000
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252
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66 store volatile half %f16.add0, ptr addrspace(1) undef
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67 store volatile half %f16.add1, ptr addrspace(1) undef
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68 store volatile float %f32.add, ptr addrspace(1) undef
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150
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69 ret void
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70 }
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71
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72 define amdgpu_kernel void @add_f16_1.0_multi_f32_use() #0 {
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252
|
73 %f32.val0 = load volatile float, ptr addrspace(1) undef
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74 %f32.val1 = load volatile float, ptr addrspace(1) undef
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75 %f32.val = load volatile float, ptr addrspace(1) undef
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|
150
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76 %f32.add0 = fadd float %f32.val0, 1.0
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77 %f32.add1 = fadd float %f32.val1, 1.0
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252
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78 store volatile float %f32.add0, ptr addrspace(1) undef
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79 store volatile float %f32.add1, ptr addrspace(1) undef
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|
150
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80 ret void
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|
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81 }
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82
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83 define amdgpu_kernel void @add_f16_1.0_other_high_bits_multi_f16_use() #0 {
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252
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84 %f16.val0 = load volatile half, ptr addrspace(1) undef
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85 %f16.val1 = load volatile half, ptr addrspace(1) undef
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86 %f32.val = load volatile half, ptr addrspace(1) undef
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|
150
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87 %f16.add0 = fadd half %f16.val0, 0xH3C00
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88 %f32.add = fadd half %f32.val, 1.000000e+00
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252
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89 store volatile half %f16.add0, ptr addrspace(1) undef
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90 store volatile half %f32.add, ptr addrspace(1) undef
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|
150
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91 ret void
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|
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92 }
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93
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|
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94 define amdgpu_kernel void @add_f16_1.0_other_high_bits_use_f16_f32() #0 {
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252
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95 %f16.val0 = load volatile half, ptr addrspace(1) undef
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96 %f16.val1 = load volatile half, ptr addrspace(1) undef
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97 %f32.val = load volatile half, ptr addrspace(1) undef
|
|
150
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98 %f16.add0 = fadd half %f16.val0, 0xH3C00
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99 %f32.add = fadd half %f32.val, 1.000000e+00
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252
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100 store volatile half %f16.add0, ptr addrspace(1) undef
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101 store volatile half %f32.add, ptr addrspace(1) undef
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|
150
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102 ret void
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103 }
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104
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|
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105 attributes #0 = { nounwind }
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106
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|
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107 ...
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|
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108 ---
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|
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109
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|
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110 # f32 1.0 with a single use should be folded as the low 32-bits of a
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111 # literal constant.
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112
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113 # CHECK-LABEL: name: add_f32_1.0_one_f16_use
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221
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114 # CHECK: %13:vgpr_32 = V_ADD_F16_e32 1065353216, killed %11, implicit $mode, implicit $exec
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|
150
|
115
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116 name: add_f32_1.0_one_f16_use
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117 alignment: 1
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118 exposesReturnsTwice: false
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119 legalized: false
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120 regBankSelected: false
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121 selected: false
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122 tracksRegLiveness: true
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123 registers:
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124 - { id: 0, class: sreg_64 }
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125 - { id: 1, class: sreg_32 }
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126 - { id: 2, class: sgpr_32 }
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127 - { id: 3, class: vgpr_32 }
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128 - { id: 4, class: sreg_64 }
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129 - { id: 5, class: sreg_32 }
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130 - { id: 6, class: sreg_64 }
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131 - { id: 7, class: sreg_32 }
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132 - { id: 8, class: sreg_32 }
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133 - { id: 9, class: sreg_32 }
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134 - { id: 10, class: sgpr_128 }
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135 - { id: 11, class: vgpr_32 }
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136 - { id: 12, class: vgpr_32 }
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137 - { id: 13, class: vgpr_32 }
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138 frameInfo:
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139 isFrameAddressTaken: false
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140 isReturnAddressTaken: false
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141 hasStackMap: false
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142 hasPatchPoint: false
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143 stackSize: 0
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144 offsetAdjustment: 0
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145 maxAlignment: 0
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146 adjustsStack: false
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147 hasCalls: false
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148 maxCallFrameSize: 0
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149 hasOpaqueSPAdjustment: false
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150 hasVAStart: false
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151 hasMustTailInVarArgFunc: false
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152 body: |
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153 bb.0 (%ir-block.0):
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154 %4 = IMPLICIT_DEF
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155 %5 = COPY %4.sub1
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156 %6 = IMPLICIT_DEF
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157 %7 = COPY %6.sub0
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158 %8 = S_MOV_B32 61440
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159 %9 = S_MOV_B32 -1
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160 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
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252
|
161 %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
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|
150
|
162 %12 = V_MOV_B32_e32 1065353216, implicit $exec
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|
221
|
163 %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit $mode, implicit $exec
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252
|
164 BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
150
|
165 S_ENDPGM 0
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166
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|
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167 ...
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|
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168 ---
|
|
|
169 # Materialized f32 inline immediate should not be folded into the f16
|
|
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170 # operands
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|
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171
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|
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172 # CHECK-LABEL: name: add_f32_1.0_multi_f16_use
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|
236
|
173 # CHECK: %14:vgpr_32 = V_ADD_F16_e32 1065353216, killed %11, implicit $mode, implicit $exec
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|
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174 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, killed %12, implicit $mode, implicit $exec
|
|
150
|
175
|
|
|
176
|
|
|
177 name: add_f32_1.0_multi_f16_use
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|
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178 alignment: 1
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|
|
179 exposesReturnsTwice: false
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|
|
180 legalized: false
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|
|
181 regBankSelected: false
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|
|
182 selected: false
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|
|
183 tracksRegLiveness: true
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|
|
184 registers:
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|
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185 - { id: 0, class: sreg_64 }
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|
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186 - { id: 1, class: sreg_32 }
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|
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187 - { id: 2, class: sgpr_32 }
|
|
|
188 - { id: 3, class: vgpr_32 }
|
|
|
189 - { id: 4, class: sreg_64 }
|
|
|
190 - { id: 5, class: sreg_32 }
|
|
|
191 - { id: 6, class: sreg_64 }
|
|
|
192 - { id: 7, class: sreg_32 }
|
|
|
193 - { id: 8, class: sreg_32 }
|
|
|
194 - { id: 9, class: sreg_32 }
|
|
|
195 - { id: 10, class: sgpr_128 }
|
|
|
196 - { id: 11, class: vgpr_32 }
|
|
|
197 - { id: 12, class: vgpr_32 }
|
|
|
198 - { id: 13, class: vgpr_32 }
|
|
|
199 - { id: 14, class: vgpr_32 }
|
|
|
200 - { id: 15, class: vgpr_32 }
|
|
|
201 frameInfo:
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|
|
202 isFrameAddressTaken: false
|
|
|
203 isReturnAddressTaken: false
|
|
|
204 hasStackMap: false
|
|
|
205 hasPatchPoint: false
|
|
|
206 stackSize: 0
|
|
|
207 offsetAdjustment: 0
|
|
|
208 maxAlignment: 0
|
|
|
209 adjustsStack: false
|
|
|
210 hasCalls: false
|
|
|
211 maxCallFrameSize: 0
|
|
|
212 hasOpaqueSPAdjustment: false
|
|
|
213 hasVAStart: false
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|
|
214 hasMustTailInVarArgFunc: false
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|
|
215 body: |
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|
|
216 bb.0 (%ir-block.0):
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|
|
217 %4 = IMPLICIT_DEF
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|
|
218 %5 = COPY %4.sub1
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219 %6 = IMPLICIT_DEF
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|
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220 %7 = COPY %6.sub0
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|
|
221 %8 = S_MOV_B32 61440
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|
|
222 %9 = S_MOV_B32 -1
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|
|
223 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
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|
252
|
224 %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
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|
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225 %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
150
|
226 %13 = V_MOV_B32_e32 1065353216, implicit $exec
|
|
221
|
227 %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $mode, implicit $exec
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|
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228 %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $mode, implicit $exec
|
|
252
|
229 BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
230 BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
150
|
231 S_ENDPGM 0
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|
|
232
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|
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233 ...
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|
|
234 ---
|
|
|
235
|
|
|
236 # f32 1.0 should be folded into the single f32 use as an inline
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|
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237 # immediate, and folded into the single f16 use as a literal constant
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|
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238
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|
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239 # CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use
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|
221
|
240 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, %11, implicit $mode, implicit $exec
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|
|
241 # CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $mode, implicit $exec
|
|
150
|
242
|
|
|
243 name: add_f32_1.0_one_f32_use_one_f16_use
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|
|
244 alignment: 1
|
|
|
245 exposesReturnsTwice: false
|
|
|
246 legalized: false
|
|
|
247 regBankSelected: false
|
|
|
248 selected: false
|
|
|
249 tracksRegLiveness: true
|
|
|
250 registers:
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|
|
251 - { id: 0, class: sreg_64 }
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|
|
252 - { id: 1, class: sreg_32 }
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|
|
253 - { id: 2, class: sgpr_32 }
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|
|
254 - { id: 3, class: vgpr_32 }
|
|
|
255 - { id: 4, class: sreg_64 }
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|
|
256 - { id: 5, class: sreg_32 }
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|
|
257 - { id: 6, class: sreg_64 }
|
|
|
258 - { id: 7, class: sreg_32 }
|
|
|
259 - { id: 8, class: sreg_32 }
|
|
|
260 - { id: 9, class: sreg_32 }
|
|
|
261 - { id: 10, class: sgpr_128 }
|
|
|
262 - { id: 11, class: vgpr_32 }
|
|
|
263 - { id: 12, class: vgpr_32 }
|
|
|
264 - { id: 13, class: vgpr_32 }
|
|
|
265 - { id: 14, class: vgpr_32 }
|
|
|
266 - { id: 15, class: vgpr_32 }
|
|
|
267 - { id: 16, class: vgpr_32 }
|
|
|
268 frameInfo:
|
|
|
269 isFrameAddressTaken: false
|
|
|
270 isReturnAddressTaken: false
|
|
|
271 hasStackMap: false
|
|
|
272 hasPatchPoint: false
|
|
|
273 stackSize: 0
|
|
|
274 offsetAdjustment: 0
|
|
|
275 maxAlignment: 0
|
|
|
276 adjustsStack: false
|
|
|
277 hasCalls: false
|
|
|
278 maxCallFrameSize: 0
|
|
|
279 hasOpaqueSPAdjustment: false
|
|
|
280 hasVAStart: false
|
|
|
281 hasMustTailInVarArgFunc: false
|
|
|
282 body: |
|
|
|
283 bb.0 (%ir-block.0):
|
|
|
284 %4 = IMPLICIT_DEF
|
|
|
285 %5 = COPY %4.sub1
|
|
|
286 %6 = IMPLICIT_DEF
|
|
|
287 %7 = COPY %6.sub0
|
|
|
288 %8 = S_MOV_B32 61440
|
|
|
289 %9 = S_MOV_B32 -1
|
|
|
290 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
|
|
252
|
291 %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
292 %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
293 %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
150
|
294 %14 = V_MOV_B32_e32 1065353216, implicit $exec
|
|
221
|
295 %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $mode, implicit $exec
|
|
|
296 %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $mode, implicit $exec
|
|
252
|
297 BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
298 BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s32) into `ptr addrspace(1) undef`)
|
|
150
|
299 S_ENDPGM 0
|
|
|
300
|
|
|
301 ...
|
|
|
302 ---
|
|
|
303
|
|
|
304 # f32 1.0 should be folded for the single f32 use as an inline
|
|
|
305 # constant, and not folded as a multi-use literal for the f16 cases
|
|
|
306
|
|
|
307 # CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
|
|
236
|
308 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, %11, implicit $mode, implicit $exec
|
|
|
309 # CHECK: %16:vgpr_32 = V_ADD_F16_e32 1065353216, %12, implicit $mode, implicit $exec
|
|
221
|
310 # CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $mode, implicit $exec
|
|
150
|
311
|
|
|
312 name: add_f32_1.0_one_f32_use_multi_f16_use
|
|
|
313 alignment: 1
|
|
|
314 exposesReturnsTwice: false
|
|
|
315 legalized: false
|
|
|
316 regBankSelected: false
|
|
|
317 selected: false
|
|
|
318 tracksRegLiveness: true
|
|
|
319 registers:
|
|
|
320 - { id: 0, class: sreg_64 }
|
|
|
321 - { id: 1, class: sreg_32 }
|
|
|
322 - { id: 2, class: sgpr_32 }
|
|
|
323 - { id: 3, class: vgpr_32 }
|
|
|
324 - { id: 4, class: sreg_64 }
|
|
|
325 - { id: 5, class: sreg_32 }
|
|
|
326 - { id: 6, class: sreg_64 }
|
|
|
327 - { id: 7, class: sreg_32 }
|
|
|
328 - { id: 8, class: sreg_32 }
|
|
|
329 - { id: 9, class: sreg_32 }
|
|
|
330 - { id: 10, class: sgpr_128 }
|
|
|
331 - { id: 11, class: vgpr_32 }
|
|
|
332 - { id: 12, class: vgpr_32 }
|
|
|
333 - { id: 13, class: vgpr_32 }
|
|
|
334 - { id: 14, class: vgpr_32 }
|
|
|
335 - { id: 15, class: vgpr_32 }
|
|
|
336 - { id: 16, class: vgpr_32 }
|
|
|
337 - { id: 17, class: vgpr_32 }
|
|
|
338 frameInfo:
|
|
|
339 isFrameAddressTaken: false
|
|
|
340 isReturnAddressTaken: false
|
|
|
341 hasStackMap: false
|
|
|
342 hasPatchPoint: false
|
|
|
343 stackSize: 0
|
|
|
344 offsetAdjustment: 0
|
|
|
345 maxAlignment: 0
|
|
|
346 adjustsStack: false
|
|
|
347 hasCalls: false
|
|
|
348 maxCallFrameSize: 0
|
|
|
349 hasOpaqueSPAdjustment: false
|
|
|
350 hasVAStart: false
|
|
|
351 hasMustTailInVarArgFunc: false
|
|
|
352 body: |
|
|
|
353 bb.0 (%ir-block.0):
|
|
|
354 %4 = IMPLICIT_DEF
|
|
|
355 %5 = COPY %4.sub1
|
|
|
356 %6 = IMPLICIT_DEF
|
|
|
357 %7 = COPY %6.sub0
|
|
|
358 %8 = S_MOV_B32 61440
|
|
|
359 %9 = S_MOV_B32 -1
|
|
|
360 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
|
|
252
|
361 %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
362 %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
363 %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
150
|
364 %14 = V_MOV_B32_e32 1065353216, implicit $exec
|
|
221
|
365 %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $mode, implicit $exec
|
|
|
366 %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $mode, implicit $exec
|
|
|
367 %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $mode, implicit $exec
|
|
252
|
368 BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
369 BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
370 BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s32) into `ptr addrspace(1) undef`)
|
|
150
|
371 S_ENDPGM 0
|
|
|
372
|
|
|
373 ...
|
|
|
374 ---
|
|
|
375 # CHECK-LABEL: name: add_i32_1_multi_f16_use
|
|
221
|
376 # CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit $mode, implicit $exec
|
|
|
377 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit $mode, implicit $exec
|
|
150
|
378
|
|
|
379
|
|
|
380 name: add_i32_1_multi_f16_use
|
|
|
381 alignment: 1
|
|
|
382 exposesReturnsTwice: false
|
|
|
383 legalized: false
|
|
|
384 regBankSelected: false
|
|
|
385 selected: false
|
|
|
386 tracksRegLiveness: true
|
|
|
387 registers:
|
|
|
388 - { id: 0, class: sreg_64 }
|
|
|
389 - { id: 1, class: sreg_32 }
|
|
|
390 - { id: 2, class: sgpr_32 }
|
|
|
391 - { id: 3, class: vgpr_32 }
|
|
|
392 - { id: 4, class: sreg_64 }
|
|
|
393 - { id: 5, class: sreg_32 }
|
|
|
394 - { id: 6, class: sreg_64 }
|
|
|
395 - { id: 7, class: sreg_32 }
|
|
|
396 - { id: 8, class: sreg_32 }
|
|
|
397 - { id: 9, class: sreg_32 }
|
|
|
398 - { id: 10, class: sgpr_128 }
|
|
|
399 - { id: 11, class: vgpr_32 }
|
|
|
400 - { id: 12, class: vgpr_32 }
|
|
|
401 - { id: 13, class: vgpr_32 }
|
|
|
402 - { id: 14, class: vgpr_32 }
|
|
|
403 - { id: 15, class: vgpr_32 }
|
|
|
404 frameInfo:
|
|
|
405 isFrameAddressTaken: false
|
|
|
406 isReturnAddressTaken: false
|
|
|
407 hasStackMap: false
|
|
|
408 hasPatchPoint: false
|
|
|
409 stackSize: 0
|
|
|
410 offsetAdjustment: 0
|
|
|
411 maxAlignment: 0
|
|
|
412 adjustsStack: false
|
|
|
413 hasCalls: false
|
|
|
414 maxCallFrameSize: 0
|
|
|
415 hasOpaqueSPAdjustment: false
|
|
|
416 hasVAStart: false
|
|
|
417 hasMustTailInVarArgFunc: false
|
|
|
418 body: |
|
|
|
419 bb.0 (%ir-block.0):
|
|
|
420 %4 = IMPLICIT_DEF
|
|
|
421 %5 = COPY %4.sub1
|
|
|
422 %6 = IMPLICIT_DEF
|
|
|
423 %7 = COPY %6.sub0
|
|
|
424 %8 = S_MOV_B32 61440
|
|
|
425 %9 = S_MOV_B32 -1
|
|
|
426 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
|
|
252
|
427 %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
428 %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
150
|
429 %13 = V_MOV_B32_e32 1, implicit $exec
|
|
221
|
430 %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $mode, implicit $exec
|
|
|
431 %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $mode, implicit $exec
|
|
252
|
432 BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
433 BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
150
|
434 S_ENDPGM 0
|
|
|
435
|
|
|
436 ...
|
|
|
437 ---
|
|
|
438
|
|
|
439 # CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use
|
|
221
|
440 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit $mode, implicit $exec
|
|
|
441 # CHECK: %16:vgpr_32 = V_ADD_F16_e32 -2, %12, implicit $mode, implicit $exec
|
|
|
442 # CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit $mode, implicit $exec
|
|
150
|
443
|
|
|
444 name: add_i32_m2_one_f32_use_multi_f16_use
|
|
|
445 alignment: 1
|
|
|
446 exposesReturnsTwice: false
|
|
|
447 legalized: false
|
|
|
448 regBankSelected: false
|
|
|
449 selected: false
|
|
|
450 tracksRegLiveness: true
|
|
|
451 registers:
|
|
|
452 - { id: 0, class: sreg_64 }
|
|
|
453 - { id: 1, class: sreg_32 }
|
|
|
454 - { id: 2, class: sgpr_32 }
|
|
|
455 - { id: 3, class: vgpr_32 }
|
|
|
456 - { id: 4, class: sreg_64 }
|
|
|
457 - { id: 5, class: sreg_32 }
|
|
|
458 - { id: 6, class: sreg_64 }
|
|
|
459 - { id: 7, class: sreg_32 }
|
|
|
460 - { id: 8, class: sreg_32 }
|
|
|
461 - { id: 9, class: sreg_32 }
|
|
|
462 - { id: 10, class: sgpr_128 }
|
|
|
463 - { id: 11, class: vgpr_32 }
|
|
|
464 - { id: 12, class: vgpr_32 }
|
|
|
465 - { id: 13, class: vgpr_32 }
|
|
|
466 - { id: 14, class: vgpr_32 }
|
|
|
467 - { id: 15, class: vgpr_32 }
|
|
|
468 - { id: 16, class: vgpr_32 }
|
|
|
469 - { id: 17, class: vgpr_32 }
|
|
|
470 frameInfo:
|
|
|
471 isFrameAddressTaken: false
|
|
|
472 isReturnAddressTaken: false
|
|
|
473 hasStackMap: false
|
|
|
474 hasPatchPoint: false
|
|
|
475 stackSize: 0
|
|
|
476 offsetAdjustment: 0
|
|
|
477 maxAlignment: 0
|
|
|
478 adjustsStack: false
|
|
|
479 hasCalls: false
|
|
|
480 maxCallFrameSize: 0
|
|
|
481 hasOpaqueSPAdjustment: false
|
|
|
482 hasVAStart: false
|
|
|
483 hasMustTailInVarArgFunc: false
|
|
|
484 body: |
|
|
|
485 bb.0 (%ir-block.0):
|
|
|
486 %4 = IMPLICIT_DEF
|
|
|
487 %5 = COPY %4.sub1
|
|
|
488 %6 = IMPLICIT_DEF
|
|
|
489 %7 = COPY %6.sub0
|
|
|
490 %8 = S_MOV_B32 61440
|
|
|
491 %9 = S_MOV_B32 -1
|
|
|
492 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
|
|
252
|
493 %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
494 %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
495 %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
150
|
496 %14 = V_MOV_B32_e32 -2, implicit $exec
|
|
221
|
497 %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $mode, implicit $exec
|
|
|
498 %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $mode, implicit $exec
|
|
|
499 %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $mode, implicit $exec
|
|
252
|
500 BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
501 BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
502 BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s32) into `ptr addrspace(1) undef`)
|
|
150
|
503 S_ENDPGM 0
|
|
|
504
|
|
|
505 ...
|
|
|
506 ---
|
|
|
507
|
|
|
508 # f32 1.0 should be folded for the single f32 use as an inline
|
|
|
509 # constant, and not folded as a multi-use literal for the f16 cases
|
|
|
510
|
|
|
511 # CHECK-LABEL: name: add_f16_1.0_multi_f32_use
|
|
236
|
512 # CHECK: %14:vgpr_32 = V_ADD_F32_e32 15360, %11, implicit $mode, implicit $exec
|
|
|
513 # CHECK: %15:vgpr_32 = V_ADD_F32_e32 15360, %12, implicit $mode, implicit $exec
|
|
150
|
514
|
|
|
515 name: add_f16_1.0_multi_f32_use
|
|
|
516 alignment: 1
|
|
|
517 exposesReturnsTwice: false
|
|
|
518 legalized: false
|
|
|
519 regBankSelected: false
|
|
|
520 selected: false
|
|
|
521 tracksRegLiveness: true
|
|
|
522 registers:
|
|
|
523 - { id: 0, class: sreg_64 }
|
|
|
524 - { id: 1, class: sreg_32 }
|
|
|
525 - { id: 2, class: sgpr_32 }
|
|
|
526 - { id: 3, class: vgpr_32 }
|
|
|
527 - { id: 4, class: sreg_64 }
|
|
|
528 - { id: 5, class: sreg_32 }
|
|
|
529 - { id: 6, class: sreg_64 }
|
|
|
530 - { id: 7, class: sreg_32 }
|
|
|
531 - { id: 8, class: sreg_32 }
|
|
|
532 - { id: 9, class: sreg_32 }
|
|
|
533 - { id: 10, class: sgpr_128 }
|
|
|
534 - { id: 11, class: vgpr_32 }
|
|
|
535 - { id: 12, class: vgpr_32 }
|
|
|
536 - { id: 13, class: vgpr_32 }
|
|
|
537 - { id: 14, class: vgpr_32 }
|
|
|
538 - { id: 15, class: vgpr_32 }
|
|
|
539 frameInfo:
|
|
|
540 isFrameAddressTaken: false
|
|
|
541 isReturnAddressTaken: false
|
|
|
542 hasStackMap: false
|
|
|
543 hasPatchPoint: false
|
|
|
544 stackSize: 0
|
|
|
545 offsetAdjustment: 0
|
|
|
546 maxAlignment: 0
|
|
|
547 adjustsStack: false
|
|
|
548 hasCalls: false
|
|
|
549 maxCallFrameSize: 0
|
|
|
550 hasOpaqueSPAdjustment: false
|
|
|
551 hasVAStart: false
|
|
|
552 hasMustTailInVarArgFunc: false
|
|
|
553 body: |
|
|
|
554 bb.0 (%ir-block.0):
|
|
|
555 %4 = IMPLICIT_DEF
|
|
|
556 %5 = COPY %4.sub1
|
|
|
557 %6 = IMPLICIT_DEF
|
|
|
558 %7 = COPY %6.sub0
|
|
|
559 %8 = S_MOV_B32 61440
|
|
|
560 %9 = S_MOV_B32 -1
|
|
|
561 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
|
|
252
|
562 %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
|
563 %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
150
|
564 %13 = V_MOV_B32_e32 15360, implicit $exec
|
|
221
|
565 %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $mode, implicit $exec
|
|
|
566 %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit $mode, implicit $exec
|
|
252
|
567 BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s32) into `ptr addrspace(1) undef`)
|
|
|
568 BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s32) into `ptr addrspace(1) undef`)
|
|
150
|
569 S_ENDPGM 0
|
|
|
570
|
|
|
571 ...
|
|
|
572 ---
|
|
|
573
|
|
|
574 # The low 16-bits are an inline immediate, but the high bits are junk
|
|
|
575
|
|
|
576 # CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
|
|
236
|
577 # CHECK: %14:vgpr_32 = V_ADD_F16_e32 80886784, %11, implicit $mode, implicit $exec
|
|
|
578 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 80886784, %12, implicit $mode, implicit $exec
|
|
150
|
579
|
|
|
580 name: add_f16_1.0_other_high_bits_multi_f16_use
|
|
|
581 alignment: 1
|
|
|
582 exposesReturnsTwice: false
|
|
|
583 legalized: false
|
|
|
584 regBankSelected: false
|
|
|
585 selected: false
|
|
|
586 tracksRegLiveness: true
|
|
|
587 registers:
|
|
|
588 - { id: 0, class: sreg_64 }
|
|
|
589 - { id: 1, class: sreg_32 }
|
|
|
590 - { id: 2, class: sgpr_32 }
|
|
|
591 - { id: 3, class: vgpr_32 }
|
|
|
592 - { id: 4, class: sreg_64 }
|
|
|
593 - { id: 5, class: sreg_32 }
|
|
|
594 - { id: 6, class: sreg_64 }
|
|
|
595 - { id: 7, class: sreg_32 }
|
|
|
596 - { id: 8, class: sreg_32 }
|
|
|
597 - { id: 9, class: sreg_32 }
|
|
|
598 - { id: 10, class: sgpr_128 }
|
|
|
599 - { id: 11, class: vgpr_32 }
|
|
|
600 - { id: 12, class: vgpr_32 }
|
|
|
601 - { id: 13, class: vgpr_32 }
|
|
|
602 - { id: 14, class: vgpr_32 }
|
|
|
603 - { id: 15, class: vgpr_32 }
|
|
|
604 frameInfo:
|
|
|
605 isFrameAddressTaken: false
|
|
|
606 isReturnAddressTaken: false
|
|
|
607 hasStackMap: false
|
|
|
608 hasPatchPoint: false
|
|
|
609 stackSize: 0
|
|
|
610 offsetAdjustment: 0
|
|
|
611 maxAlignment: 0
|
|
|
612 adjustsStack: false
|
|
|
613 hasCalls: false
|
|
|
614 maxCallFrameSize: 0
|
|
|
615 hasOpaqueSPAdjustment: false
|
|
|
616 hasVAStart: false
|
|
|
617 hasMustTailInVarArgFunc: false
|
|
|
618 body: |
|
|
|
619 bb.0 (%ir-block.0):
|
|
|
620 %4 = IMPLICIT_DEF
|
|
|
621 %5 = COPY %4.sub1
|
|
|
622 %6 = IMPLICIT_DEF
|
|
|
623 %7 = COPY %6.sub0
|
|
|
624 %8 = S_MOV_B32 61440
|
|
|
625 %9 = S_MOV_B32 -1
|
|
|
626 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
|
|
252
|
627 %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
|
628 %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
150
|
629 %13 = V_MOV_B32_e32 80886784, implicit $exec
|
|
221
|
630 %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit $mode, implicit $exec
|
|
|
631 %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $mode, implicit $exec
|
|
252
|
632 BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
|
633 BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
150
|
634 S_ENDPGM 0
|
|
|
635
|
|
|
636 ...
|
|
|
637 ---
|
|
|
638
|
|
|
639 # CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
|
|
236
|
640 # CHECK: %14:vgpr_32 = V_ADD_F32_e32 305413120, %11, implicit $mode, implicit $exec
|
|
|
641 # CHECK: %15:vgpr_32 = V_ADD_F16_e32 305413120, %12, implicit $mode, implicit $exec
|
|
150
|
642 name: add_f16_1.0_other_high_bits_use_f16_f32
|
|
|
643 alignment: 1
|
|
|
644 exposesReturnsTwice: false
|
|
|
645 legalized: false
|
|
|
646 regBankSelected: false
|
|
|
647 selected: false
|
|
|
648 tracksRegLiveness: true
|
|
|
649 registers:
|
|
|
650 - { id: 0, class: sreg_64 }
|
|
|
651 - { id: 1, class: sreg_32 }
|
|
|
652 - { id: 2, class: sgpr_32 }
|
|
|
653 - { id: 3, class: vgpr_32 }
|
|
|
654 - { id: 4, class: sreg_64 }
|
|
|
655 - { id: 5, class: sreg_32 }
|
|
|
656 - { id: 6, class: sreg_64 }
|
|
|
657 - { id: 7, class: sreg_32 }
|
|
|
658 - { id: 8, class: sreg_32 }
|
|
|
659 - { id: 9, class: sreg_32 }
|
|
|
660 - { id: 10, class: sgpr_128 }
|
|
|
661 - { id: 11, class: vgpr_32 }
|
|
|
662 - { id: 12, class: vgpr_32 }
|
|
|
663 - { id: 13, class: vgpr_32 }
|
|
|
664 - { id: 14, class: vgpr_32 }
|
|
|
665 - { id: 15, class: vgpr_32 }
|
|
|
666 frameInfo:
|
|
|
667 isFrameAddressTaken: false
|
|
|
668 isReturnAddressTaken: false
|
|
|
669 hasStackMap: false
|
|
|
670 hasPatchPoint: false
|
|
|
671 stackSize: 0
|
|
|
672 offsetAdjustment: 0
|
|
|
673 maxAlignment: 0
|
|
|
674 adjustsStack: false
|
|
|
675 hasCalls: false
|
|
|
676 maxCallFrameSize: 0
|
|
|
677 hasOpaqueSPAdjustment: false
|
|
|
678 hasVAStart: false
|
|
|
679 hasMustTailInVarArgFunc: false
|
|
|
680 body: |
|
|
|
681 bb.0 (%ir-block.0):
|
|
|
682 %4 = IMPLICIT_DEF
|
|
|
683 %5 = COPY %4.sub1
|
|
|
684 %6 = IMPLICIT_DEF
|
|
|
685 %7 = COPY %6.sub0
|
|
|
686 %8 = S_MOV_B32 61440
|
|
|
687 %9 = S_MOV_B32 -1
|
|
|
688 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
|
|
252
|
689 %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`)
|
|
|
690 %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, implicit $exec :: (volatile load (s16) from `ptr addrspace(1) undef`)
|
|
150
|
691 %13 = V_MOV_B32_e32 305413120, implicit $exec
|
|
221
|
692 %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $mode, implicit $exec
|
|
|
693 %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $mode, implicit $exec
|
|
252
|
694 BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s32) into `ptr addrspace(1) undef`)
|
|
|
695 BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, implicit $exec :: (volatile store (s16) into `ptr addrspace(1) undef`)
|
|
150
|
696 S_ENDPGM 0
|
|
|
697
|
|
|
698 ...
|
