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252
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1 ; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s
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2 ; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s
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3 ; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s
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4 ; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s
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5 ; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s
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6 ; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,LOOP %s
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7 ; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
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8 ; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP,NOLOOP-GISEL %s
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9 ; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
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10 ; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP,NOLOOP-GISEL %s
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11 ; RUN: llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -asm-verbose=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
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12 ; RUN: llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -asm-verbose=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOLOOP,NOLOOP-GISEL %s
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150
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13
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14 ; Minimum offset
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15 ; GCN-LABEL: {{^}}gws_init_offset0:
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236
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16 ; GCN-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]
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150
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17 ; GCN-DAG: s_mov_b32 m0, 0{{$}}
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18 ; GCN: v_mov_b32_e32 v0, [[BAR_NUM]]
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19 ; NOLOOP: ds_gws_init v0 gds{{$}}
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20
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236
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21 ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
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150
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22 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
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23 ; LOOP-NEXT: ds_gws_init v0 gds
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24 ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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25 ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
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26 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
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27 ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
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28 define amdgpu_kernel void @gws_init_offset0(i32 %val) #0 {
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29 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
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30 ret void
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31 }
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32
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33 ; Maximum offset
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34 ; GCN-LABEL: {{^}}gws_init_offset63:
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236
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35 ; NOLOOP-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]
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150
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36 ; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
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37 ; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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38 ; NOLOOP: ds_gws_init v0 offset:63 gds{{$}}
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39
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40
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41 ; LOOP: s_mov_b32 m0, 0{{$}}
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236
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42 ; LOOP: [[LOOP:.LBB[0-9]+_[0-9]+]]:
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150
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43 ; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
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44 ; LOOP-NEXT: ds_gws_init v0 offset:63 gds
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45 ; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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46 ; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
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47 ; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
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48 ; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
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49 define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 {
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50 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63)
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51 ret void
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52 }
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53
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54 ; FIXME: Should be able to shift directly into m0
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55 ; GCN-LABEL: {{^}}gws_init_sgpr_offset:
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236
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56 ; NOLOOP-DAG: s_load_{{dwordx2|b64}} s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]
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150
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57
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58 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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59 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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60
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61 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
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62
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63 ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
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64 ; NOLOOP: ds_gws_init [[GWS_VAL]] gds{{$}}
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65 define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 {
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66 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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67 ret void
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68 }
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69
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70 ; Variable offset in SGPR with constant add
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71 ; GCN-LABEL: {{^}}gws_init_sgpr_offset_add1:
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236
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72 ; NOLOOP-DAG: s_load_{{dwordx2|b64}} s[[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]]
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150
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73
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74 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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75 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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76
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77 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
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78
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79 ; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
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80 ; NOLOOP: ds_gws_init [[GWS_VAL]] offset:1 gds{{$}}
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81 define amdgpu_kernel void @gws_init_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {
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82 %offset = add i32 %offset.base, 1
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83 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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84 ret void
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85 }
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86
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87 ; GCN-LABEL: {{^}}gws_init_vgpr_offset:
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236
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88 ; NOLOOP-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]
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150
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89 ; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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90
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91 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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92 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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93
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94 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
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95
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96 ; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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97 ; NOLOOP: ds_gws_init v0 gds{{$}}
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98 define amdgpu_kernel void @gws_init_vgpr_offset(i32 %val) #0 {
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99 %vgpr.offset = call i32 @llvm.amdgcn.workitem.id.x()
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100 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)
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101 ret void
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102 }
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103
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104 ; Variable offset in VGPR with constant add
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105 ; GCN-LABEL: {{^}}gws_init_vgpr_offset_add:
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236
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106 ; NOLOOP-DAG: s_load_{{dword|b32}} [[BAR_NUM:s[0-9]+]]
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150
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107 ; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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108
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109 ; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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110 ; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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111
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112 ; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
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113
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114 ; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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115 ; NOLOOP: ds_gws_init v0 offset:3 gds{{$}}
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116 define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
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117 %vgpr.offset.base = call i32 @llvm.amdgcn.workitem.id.x()
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118 %vgpr.offset = add i32 %vgpr.offset.base, 3
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119 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)
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120 ret void
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121 }
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122
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123 @lds = internal unnamed_addr addrspace(3) global i32 undef
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124
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125 ; Check if m0 initialization is shared.
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126 ; GCN-LABEL: {{^}}gws_init_save_m0_init_constant_offset:
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127 ; NOLOOP: s_mov_b32 m0, 0
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128 ; NOLOOP: ds_gws_init v{{[0-9]+}} offset:10 gds
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129
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130 ; LOOP: s_mov_b32 m0, -1
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131 ; LOOP: ds_write_b32
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132 ; LOOP: s_mov_b32 m0, 0
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133 ; LOOP: s_setreg_imm32_b32
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134 ; LOOP: ds_gws_init v{{[0-9]+}} offset:10 gds
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135 ; LOOP: s_cbranch_scc1
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136
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137 ; LOOP: s_mov_b32 m0, -1
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138 ; LOOP: ds_write_b32
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139 define amdgpu_kernel void @gws_init_save_m0_init_constant_offset(i32 %val) #0 {
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252
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140 store volatile i32 1, ptr addrspace(3) @lds
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150
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141 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 10)
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252
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142 store i32 2, ptr addrspace(3) @lds
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150
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143 ret void
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144 }
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145
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146 ; GCN-LABEL: {{^}}gws_init_lgkmcnt:
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147 ; NOLOOP: s_mov_b32 m0, 0{{$}}
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148 ; NOLOOP: ds_gws_init v0 gds{{$}}
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149 ; NOLOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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150 ; NOLOOP-NEXT: s_setpc_b64
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151 define void @gws_init_lgkmcnt(i32 %val) {
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152 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
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153 ret void
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154 }
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155
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156 ; Does not imply memory fence on its own
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157 ; GCN-LABEL: {{^}}gws_init_wait_before:
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158 ; NOLOOP: s_waitcnt lgkmcnt(0)
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159 ; NOLOOP-NOT: s_waitcnt
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160 ; NOLOOP: ds_gws_init
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161 ; NOLOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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252
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162 define amdgpu_kernel void @gws_init_wait_before(i32 %val, ptr addrspace(1) %ptr) #0 {
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163 store i32 0, ptr addrspace(1) %ptr
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150
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164 call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)
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165 ret void
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166 }
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167
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168 declare void @llvm.amdgcn.ds.gws.init(i32, i32) #1
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169 declare i32 @llvm.amdgcn.workitem.id.x() #2
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170
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171 attributes #0 = { nounwind }
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172 attributes #1 = { convergent inaccessiblememonly nounwind writeonly }
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173 attributes #2 = { nounwind readnone speculatable }
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