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221
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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252
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2 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK
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221
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3
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4 define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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5 ; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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6 ; CHECK: ; %bb.0:
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7 ; CHECK-NEXT: s_mov_b32 s11, s5
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8 ; CHECK-NEXT: s_mov_b32 s10, s4
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9 ; CHECK-NEXT: s_mov_b32 s9, s3
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10 ; CHECK-NEXT: s_mov_b32 s8, s2
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11 ; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[8:11], s6 offen
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12 ; CHECK-NEXT: s_endpgm
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13 %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 24)
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14 ret void
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15 }
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16
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17 define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
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18 ; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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19 ; CHECK: ; %bb.0:
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20 ; CHECK-NEXT: s_mov_b32 s11, s5
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21 ; CHECK-NEXT: s_mov_b32 s10, s4
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22 ; CHECK-NEXT: s_mov_b32 s9, s3
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23 ; CHECK-NEXT: s_mov_b32 s8, s2
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24 ; CHECK-NEXT: buffer_atomic_add_f32 v0, off, s[8:11], s6
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25 ; CHECK-NEXT: s_endpgm
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26 %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
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27 ret void
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28 }
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29
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30 define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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31 ; CHECK-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
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32 ; CHECK: ; %bb.0:
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33 ; CHECK-NEXT: s_mov_b32 s11, s5
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34 ; CHECK-NEXT: s_mov_b32 s10, s4
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35 ; CHECK-NEXT: s_mov_b32 s9, s3
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36 ; CHECK-NEXT: s_mov_b32 s8, s2
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37 ; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[8:11], s6 offen
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38 ; CHECK-NEXT: s_endpgm
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39 %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
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40 ret void
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41 }
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42
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43 define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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44 ; CHECK-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
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45 ; CHECK: ; %bb.0:
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46 ; CHECK-NEXT: s_mov_b32 s11, s5
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47 ; CHECK-NEXT: s_mov_b32 s10, s4
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48 ; CHECK-NEXT: s_mov_b32 s9, s3
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49 ; CHECK-NEXT: s_mov_b32 s8, s2
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50 ; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, off, s[8:11], s6 offset:92
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51 ; CHECK-NEXT: s_endpgm
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52 %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 92, i32 %soffset, i32 0)
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53 ret void
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54 }
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55
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56 define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
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57 ; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
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58 ; CHECK: ; %bb.0:
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59 ; CHECK-NEXT: s_mov_b32 s11, s5
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60 ; CHECK-NEXT: s_mov_b32 s10, s4
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61 ; CHECK-NEXT: s_mov_b32 s9, s3
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62 ; CHECK-NEXT: s_mov_b32 s8, s2
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63 ; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[8:11], s6 offen slc
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64 ; CHECK-NEXT: s_endpgm
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65 %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
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66 ret void
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67 }
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68
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69 declare float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
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70 declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg) #0
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71
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72 attributes #0 = { nounwind }
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