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236
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1 ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX906
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2 ; RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX940
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3 ; RUN: llc -march=amdgcn -mcpu=gfx940 -global-isel -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX940
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150
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4 ; RUN: llc -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
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5 ; RUN: llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GFX10
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6
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7 declare i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp)
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221
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8 declare i32 @llvm.amdgcn.workitem.id.x()
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150
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9
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221
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10 ; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_clamp:
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236
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11 ; GFX9: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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150
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12 ; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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13 define amdgpu_kernel void @test_llvm_amdgcn_udot2_clamp(
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252
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14 ptr addrspace(1) %r,
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15 ptr addrspace(1) %a,
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16 ptr addrspace(1) %b,
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17 ptr addrspace(1) %c) {
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150
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18 entry:
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252
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19 %a.val = load <2 x i16>, ptr addrspace(1) %a
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20 %b.val = load <2 x i16>, ptr addrspace(1) %b
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21 %c.val = load i32, ptr addrspace(1) %c
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150
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22 %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1)
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252
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23 store i32 %r.val, ptr addrspace(1) %r
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150
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24 ret void
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25 }
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26
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221
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27 ; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_no_clamp:
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236
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28 ; GFX9: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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150
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29 ; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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30 define amdgpu_kernel void @test_llvm_amdgcn_udot2_no_clamp(
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252
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31 ptr addrspace(1) %r,
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32 ptr addrspace(1) %a,
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33 ptr addrspace(1) %b,
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34 ptr addrspace(1) %c) {
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150
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35 entry:
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252
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36 %a.val = load <2 x i16>, ptr addrspace(1) %a
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37 %b.val = load <2 x i16>, ptr addrspace(1) %b
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38 %c.val = load i32, ptr addrspace(1) %c
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150
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39 %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0)
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252
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40 store i32 %r.val, ptr addrspace(1) %r
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150
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41 ret void
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42 }
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221
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43
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44 ; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_op_sel:
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45 ; GFX906: v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}} op_sel:[0,1,0] op_sel_hi:[0,0,1]{{$}}
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236
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46 ; GFX940: v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}}{{$}}
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221
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47 ; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}} op_sel:[0,1,0] op_sel_hi:[0,0,1]{{$}}
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48 define amdgpu_kernel void @test_llvm_amdgcn_udot2_op_sel(
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252
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49 ptr addrspace(1) %r,
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50 ptr addrspace(1) %b,
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221
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51 i32 %c) {
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52 entry:
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53 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
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252
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54 %b.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %b, i32 %id
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55 %b.val = load <2 x i16>, ptr addrspace(1) %b.gep
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221
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56 %b.elt0 = extractelement <2 x i16> %b.val, i32 0
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57 %b.elt1 = extractelement <2 x i16> %b.val, i32 1
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58 %b0 = insertelement <2 x i16> undef, i16 %b.elt1, i32 0
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59 %b1 = insertelement <2 x i16> %b0, i16 %b.elt0, i32 1
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60 %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> <i16 1, i16 1>, <2 x i16> %b1, i32 %c, i1 0)
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252
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61 store i32 %r.val, ptr addrspace(1) %r
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221
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62 ret void
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63 }
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