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150
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1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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221
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3 ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN
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150
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4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2
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5 ; RUN: llc < %s -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN --check-prefix=GCN2
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6
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7 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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8
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9 ; FUNC-LABEL: {{^}}u32_mad24:
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221
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10 ; EG: MULLO_INT
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11 ; SI: s_mul_i32
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12 ; SI: s_add_i32
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13 ; VI: s_mul_{{[iu]}}32
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14 ; VI: s_add_{{[iu]}}32
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150
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15
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252
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16 define amdgpu_kernel void @u32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
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150
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17 entry:
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18 %0 = shl i32 %a, 8
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19 %a_24 = lshr i32 %0, 8
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20 %1 = shl i32 %b, 8
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21 %b_24 = lshr i32 %1, 8
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22 %2 = mul i32 %a_24, %b_24
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23 %3 = add i32 %2, %c
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252
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24 store i32 %3, ptr addrspace(1) %out
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150
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25 ret void
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26 }
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27
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28 ; FUNC-LABEL: {{^}}i16_mad24:
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29 ; The order of A and B does not matter.
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221
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30 ; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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31 ; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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150
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32 ; The result must be sign-extended
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33 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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34 ; EG: 16
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221
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35 ; GCN: s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}}
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36 ; GCN: s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}}
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37 ; GCN: s_sext_i32_i16 [[EXT:s[0-9]]], [[MAD]]
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38 ; GCN: v_mov_b32_e32 v0, [[EXT]]
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252
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39 define amdgpu_kernel void @i16_mad24(ptr addrspace(1) %out, i16 %a, i16 %b, i16 %c) {
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150
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40 entry:
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41 %0 = mul i16 %a, %b
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42 %1 = add i16 %0, %c
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43 %2 = sext i16 %1 to i32
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252
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44 store i32 %2, ptr addrspace(1) %out
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150
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45 ret void
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46 }
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47
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48 ; FIXME: Need to handle non-uniform case for function below (load without gep).
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49 ; FUNC-LABEL: {{^}}i8_mad24:
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221
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50 ; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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51 ; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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150
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52 ; The result must be sign-extended
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53 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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54 ; EG: 8
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221
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55 ; GCN: s_mul_i32 [[MUL:s[0-9]]], {{[s][0-9], [s][0-9]}}
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56 ; GCN: s_add_i32 [[MAD:s[0-9]]], [[MUL]], s{{[0-9]}}
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57 ; GCN: s_sext_i32_i8 [[EXT:s[0-9]]], [[MAD]]
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58 ; GCN: v_mov_b32_e32 v0, [[EXT]]
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252
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59 define amdgpu_kernel void @i8_mad24(ptr addrspace(1) %out, i8 %a, i8 %b, i8 %c) {
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150
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60 entry:
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61 %0 = mul i8 %a, %b
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62 %1 = add i8 %0, %c
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63 %2 = sext i8 %1 to i32
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252
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64 store i32 %2, ptr addrspace(1) %out
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|
150
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65 ret void
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66 }
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67
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68 ; This tests for a bug where the mad_u24 pattern matcher would call
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69 ; SimplifyDemandedBits on the first operand of the mul instruction
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70 ; assuming that the pattern would be matched to a 24-bit mad. This
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71 ; led to some instructions being incorrectly erased when the entire
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72 ; 24-bit mad pattern wasn't being matched.
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73
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74 ; Check that the select instruction is not deleted.
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75 ; FUNC-LABEL: {{^}}i24_i32_i32_mad:
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76 ; EG: CNDE_INT
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236
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77 ; SI: s_cselect
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221
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78 ; GCN2: s_cselect
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252
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79 define amdgpu_kernel void @i24_i32_i32_mad(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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150
|
80 entry:
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81 %0 = ashr i32 %a, 8
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82 %1 = icmp ne i32 %c, 0
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83 %2 = select i1 %1, i32 %0, i32 34
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84 %3 = mul i32 %2, %c
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85 %4 = add i32 %3, %d
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|
252
|
86 store i32 %4, ptr addrspace(1) %out
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|
150
|
87 ret void
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88 }
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89
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90 ; FUNC-LABEL: {{^}}extra_and:
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91 ; SI-NOT: v_and
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221
|
92 ; SI: s_mul_i32
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93 ; SI: s_mul_i32
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94 ; SI: s_add_i32
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95 ; SI: s_add_i32
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252
|
96 define amdgpu_kernel void @extra_and(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) {
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|
150
|
97 bb:
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98 br label %bb4
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99
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100 bb4: ; preds = %bb4, %bb
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101 %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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102 %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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103 %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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104 %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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105 %tmp8 = and i32 %tmp7, 16777215
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106 %tmp9 = and i32 %tmp6, 16777215
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107 %tmp10 = and i32 %tmp5, 16777215
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108 %tmp11 = and i32 %tmp, 16777215
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109 %tmp12 = mul i32 %tmp8, %tmp11
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110 %tmp13 = add i32 %arg2, %tmp12
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111 %tmp14 = mul i32 %tmp9, %tmp11
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112 %tmp15 = add i32 %arg3, %tmp14
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113 %tmp16 = add nuw nsw i32 %tmp13, %tmp15
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114 %tmp17 = icmp eq i32 %tmp16, 8
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115 br i1 %tmp17, label %bb18, label %bb4
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116
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117 bb18: ; preds = %bb4
|
|
252
|
118 store i32 %tmp16, ptr addrspace(1) %arg
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|
150
|
119 ret void
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120 }
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121
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|
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122 ; FUNC-LABEL: {{^}}dont_remove_shift
|
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221
|
123 ; SI: s_lshr
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124 ; SI: s_mul_i32
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125 ; SI: s_mul_i32
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126 ; SI: s_add_i32
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127 ; SI: s_add_i32
|
|
252
|
128 define amdgpu_kernel void @dont_remove_shift(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) {
|
|
150
|
129 bb:
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|
130 br label %bb4
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131
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132 bb4: ; preds = %bb4, %bb
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133 %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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134 %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
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135 %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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136 %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
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137 %tmp8 = lshr i32 %tmp7, 8
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138 %tmp9 = lshr i32 %tmp6, 8
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139 %tmp10 = lshr i32 %tmp5, 8
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140 %tmp11 = lshr i32 %tmp, 8
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141 %tmp12 = mul i32 %tmp8, %tmp11
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|
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142 %tmp13 = add i32 %arg2, %tmp12
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143 %tmp14 = mul i32 %tmp9, %tmp11
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144 %tmp15 = add i32 %arg3, %tmp14
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|
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145 %tmp16 = add nuw nsw i32 %tmp13, %tmp15
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|
|
146 %tmp17 = icmp eq i32 %tmp16, 8
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|
|
147 br i1 %tmp17, label %bb18, label %bb4
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|
|
148
|
|
|
149 bb18: ; preds = %bb4
|
|
252
|
150 store i32 %tmp16, ptr addrspace(1) %arg
|
|
150
|
151 ret void
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|
|
152 }
|
|
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153
|
|
|
154 ; FUNC-LABEL: {{^}}i8_mad_sat_16:
|
|
221
|
155 ; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
|
|
|
156 ; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
|
|
150
|
157 ; The result must be sign-extended
|
|
|
158 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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|
|
159 ; EG: 8
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|
|
160 ; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
|
|
252
|
161 ; SI: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
|
|
|
162 ; SI: v_med3_i32 v{{[0-9]}}, [[EXT]],
|
|
150
|
163 ; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
|
|
252
|
164 ; VI: v_max_i16_e32 [[MAX:v[0-9]]], 0xff80, [[MAD]]
|
|
|
165 ; VI: v_min_i16_e32 {{v[0-9]}}, 0x7f, [[MAX]]
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|
|
166 define amdgpu_kernel void @i8_mad_sat_16(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(5) %idx) {
|
|
150
|
167 entry:
|
|
252
|
168 %retval.0.i = load i64, ptr addrspace(5) %idx
|
|
|
169 %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %in0, i64 %retval.0.i
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|
|
170 %arrayidx2 = getelementptr inbounds i8, ptr addrspace(1) %in1, i64 %retval.0.i
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|
|
171 %arrayidx4 = getelementptr inbounds i8, ptr addrspace(1) %in2, i64 %retval.0.i
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|
|
172 %l1 = load i8, ptr addrspace(1) %arrayidx, align 1
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|
|
173 %l2 = load i8, ptr addrspace(1) %arrayidx2, align 1
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|
|
174 %l3 = load i8, ptr addrspace(1) %arrayidx4, align 1
|
|
150
|
175 %conv1.i = sext i8 %l1 to i16
|
|
|
176 %conv3.i = sext i8 %l2 to i16
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|
|
177 %conv5.i = sext i8 %l3 to i16
|
|
|
178 %mul.i.i.i = mul nsw i16 %conv3.i, %conv1.i
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|
|
179 %add.i.i = add i16 %mul.i.i.i, %conv5.i
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|
|
180 %c4 = icmp sgt i16 %add.i.i, -128
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|
|
181 %cond.i.i = select i1 %c4, i16 %add.i.i, i16 -128
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|
|
182 %c5 = icmp slt i16 %cond.i.i, 127
|
|
|
183 %cond13.i.i = select i1 %c5, i16 %cond.i.i, i16 127
|
|
|
184 %conv8.i = trunc i16 %cond13.i.i to i8
|
|
252
|
185 %arrayidx7 = getelementptr inbounds i8, ptr addrspace(1) %out, i64 %retval.0.i
|
|
|
186 store i8 %conv8.i, ptr addrspace(1) %arrayidx7, align 1
|
|
150
|
187 ret void
|
|
|
188 }
|
|
|
189
|
|
|
190 ; FUNC-LABEL: {{^}}i8_mad_32:
|
|
221
|
191 ; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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|
|
192 ; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
|
|
150
|
193 ; The result must be sign-extended
|
|
|
194 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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|
|
195 ; EG: 8
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|
|
196 ; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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|
|
197 ; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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|
|
198 ; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
|
|
252
|
199 define amdgpu_kernel void @i8_mad_32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) {
|
|
150
|
200 entry:
|
|
252
|
201 %retval.0.i = load i64, ptr addrspace(5) %idx
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|
|
202 %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i
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|
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203 %arrayidx2 = getelementptr inbounds i8, ptr addrspace(1) %b, i64 %retval.0.i
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204 %arrayidx4 = getelementptr inbounds i8, ptr addrspace(1) %c, i64 %retval.0.i
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205 %la = load i8, ptr addrspace(1) %arrayidx, align 1
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|
|
206 %lb = load i8, ptr addrspace(1) %arrayidx2, align 1
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|
|
207 %lc = load i8, ptr addrspace(1) %arrayidx4, align 1
|
|
150
|
208 %exta = sext i8 %la to i16
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|
|
209 %extb = sext i8 %lb to i16
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|
|
210 %extc = sext i8 %lc to i16
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|
|
211 %mul = mul i16 %exta, %extb
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|
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212 %mad = add i16 %mul, %extc
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|
|
213 %mad_ext = sext i16 %mad to i32
|
|
252
|
214 store i32 %mad_ext, ptr addrspace(1) %out
|
|
150
|
215 ret void
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|
|
216 }
|
|
|
217
|
|
|
218 ; FUNC-LABEL: {{^}}i8_mad_64:
|
|
221
|
219 ; EG: MULLO_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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|
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220 ; EG: ADD_INT {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
|
|
150
|
221 ; The result must be sign-extended
|
|
|
222 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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|
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223 ; EG: 8
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224 ; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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|
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225 ; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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|
|
226 ; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
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|
252
|
227 define amdgpu_kernel void @i8_mad_64(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) {
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|
150
|
228 entry:
|
|
252
|
229 %retval.0.i = load i64, ptr addrspace(5) %idx
|
|
|
230 %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i
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|
231 %arrayidx2 = getelementptr inbounds i8, ptr addrspace(1) %b, i64 %retval.0.i
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|
232 %arrayidx4 = getelementptr inbounds i8, ptr addrspace(1) %c, i64 %retval.0.i
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|
233 %la = load i8, ptr addrspace(1) %arrayidx, align 1
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234 %lb = load i8, ptr addrspace(1) %arrayidx2, align 1
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|
|
235 %lc = load i8, ptr addrspace(1) %arrayidx4, align 1
|
|
150
|
236 %exta = sext i8 %la to i16
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|
|
237 %extb = sext i8 %lb to i16
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|
|
238 %extc = sext i8 %lc to i16
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|
|
239 %mul = mul i16 %exta, %extb
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|
|
240 %mad = add i16 %mul, %extc
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|
|
241 %mad_ext = sext i16 %mad to i64
|
|
252
|
242 store i64 %mad_ext, ptr addrspace(1) %out
|
|
150
|
243 ret void
|
|
|
244 }
|
|
|
245
|
|
|
246 ; The ands are asserting the high bits are 0. SimplifyDemandedBits on
|
|
|
247 ; the adds would remove the ands before the target combine on the mul
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|
|
248 ; had a chance to form mul24. The mul combine would then see
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|
|
249 ; extractelement with no known bits and fail. All of the mul/add
|
|
|
250 ; combos in this loop should form v_mad_u32_u24.
|
|
|
251
|
|
|
252 ; FUNC-LABEL: {{^}}mad24_known_bits_destroyed:
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|
|
253 ; GCN: v_mad_u32_u24
|
|
|
254 ; GCN: v_mad_u32_u24
|
|
|
255 ; GCN: v_mad_u32_u24
|
|
|
256 ; GCN: v_mad_u32_u24
|
|
|
257 ; GCN: v_mad_u32_u24
|
|
|
258 ; GCN: v_mad_u32_u24
|
|
|
259 ; GCN: v_mad_u32_u24
|
|
|
260 ; GCN: v_mad_u32_u24
|
|
252
|
261 define void @mad24_known_bits_destroyed(i32 %arg, <4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3, i32 %arg4, i32 %arg5, i32 %arg6, ptr addrspace(1) %arg7, ptr addrspace(1) %arg8) #0 {
|
|
150
|
262 bb:
|
|
|
263 %tmp = and i32 %arg4, 16777215
|
|
|
264 %tmp9 = extractelement <4 x i32> %arg1, i64 1
|
|
|
265 %tmp10 = extractelement <4 x i32> %arg3, i64 1
|
|
|
266 %tmp11 = and i32 %tmp9, 16777215
|
|
|
267 %tmp12 = extractelement <4 x i32> %arg1, i64 2
|
|
|
268 %tmp13 = extractelement <4 x i32> %arg3, i64 2
|
|
|
269 %tmp14 = and i32 %tmp12, 16777215
|
|
|
270 %tmp15 = extractelement <4 x i32> %arg1, i64 3
|
|
|
271 %tmp16 = extractelement <4 x i32> %arg3, i64 3
|
|
|
272 %tmp17 = and i32 %tmp15, 16777215
|
|
|
273 br label %bb19
|
|
|
274
|
|
|
275 bb18: ; preds = %bb19
|
|
|
276 ret void
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277
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278 bb19: ; preds = %bb19, %bb
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279 %tmp20 = phi i32 [ %arg, %bb ], [ %tmp40, %bb19 ]
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280 %tmp21 = phi i32 [ 0, %bb ], [ %tmp54, %bb19 ]
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281 %tmp22 = phi <4 x i32> [ %arg2, %bb ], [ %tmp53, %bb19 ]
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282 %tmp23 = and i32 %tmp20, 16777215
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283 %tmp24 = mul i32 %tmp23, %tmp
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284 %tmp25 = add i32 %tmp24, %arg5
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285 %tmp26 = extractelement <4 x i32> %tmp22, i64 1
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286 %tmp27 = and i32 %tmp26, 16777215
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287 %tmp28 = mul i32 %tmp27, %tmp11
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288 %tmp29 = add i32 %tmp28, %tmp10
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289 %tmp30 = extractelement <4 x i32> %tmp22, i64 2
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290 %tmp31 = and i32 %tmp30, 16777215
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291 %tmp32 = mul i32 %tmp31, %tmp14
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292 %tmp33 = add i32 %tmp32, %tmp13
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293 %tmp34 = extractelement <4 x i32> %tmp22, i64 3
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294 %tmp35 = and i32 %tmp34, 16777215
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295 %tmp36 = mul i32 %tmp35, %tmp17
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296 %tmp37 = add i32 %tmp36, %tmp16
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297 %tmp38 = and i32 %tmp25, 16777215
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298 %tmp39 = mul i32 %tmp38, %tmp
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299 %tmp40 = add i32 %tmp39, %arg5
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252
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300 store i32 %tmp40, ptr addrspace(1) %arg7
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150
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301 %tmp41 = insertelement <4 x i32> undef, i32 %tmp40, i32 0
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302 %tmp42 = and i32 %tmp29, 16777215
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303 %tmp43 = mul i32 %tmp42, %tmp11
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304 %tmp44 = add i32 %tmp43, %tmp10
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305 %tmp45 = insertelement <4 x i32> %tmp41, i32 %tmp44, i32 1
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306 %tmp46 = and i32 %tmp33, 16777215
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307 %tmp47 = mul i32 %tmp46, %tmp14
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308 %tmp48 = add i32 %tmp47, %tmp13
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309 %tmp49 = insertelement <4 x i32> %tmp45, i32 %tmp48, i32 2
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310 %tmp50 = and i32 %tmp37, 16777215
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311 %tmp51 = mul i32 %tmp50, %tmp17
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312 %tmp52 = add i32 %tmp51, %tmp16
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313 %tmp53 = insertelement <4 x i32> %tmp49, i32 %tmp52, i32 3
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252
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314 store <4 x i32> %tmp53, ptr addrspace(1) %arg8
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150
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315 %tmp54 = add nuw nsw i32 %tmp21, 1
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316 %tmp55 = icmp eq i32 %tmp54, %arg6
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317 br i1 %tmp55, label %bb18, label %bb19
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318 }
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319
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320 attributes #0 = { norecurse nounwind }
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