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252
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1 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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3 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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4 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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150
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5
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6 ; GCN-LABEL: {{^}}vgpr:
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7 ; GCN-DAG: v_mov_b32_e32 v1, v0
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8 ; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm
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9 ; GCN: s_waitcnt expcnt(0)
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10 ; GCN: v_add_f32_e32 v0, 1.0, v1
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11 ; GCN-NOT: s_endpgm
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252
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12 define amdgpu_vs { float, float } @vgpr(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
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150
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13 bb:
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14 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
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15 %x = fadd float %arg3, 1.000000e+00
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16 %a = insertvalue { float, float } undef, float %x, 0
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17 %b = insertvalue { float, float } %a, float %arg3, 1
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18 ret { float, float } %b
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19 }
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20
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21 ; GCN-LABEL: {{^}}vgpr_literal:
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22 ; GCN: exp mrt0 v0, v0, v0, v0 done vm
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23
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24 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
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25 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
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26 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
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27 ; GCN-DAG: v_mov_b32_e32 v3, -1.0
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28 ; GCN-DAG: s_waitcnt expcnt(0)
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29 ; GCN-NOT: s_endpgm
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252
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30 define amdgpu_vs { float, float, float, float } @vgpr_literal(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
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150
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31 bb:
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32 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
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33 ret { float, float, float, float } { float 1.000000e+00, float 2.000000e+00, float 4.000000e+00, float -1.000000e+00 }
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34 }
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35
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36 ; GCN: .long 165580
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37 ; GCN-NEXT: .long 562
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38 ; GCN-NEXT: .long 165584
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39 ; GCN-NEXT: .long 562
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40 ; GCN-LABEL: {{^}}vgpr_ps_addr0:
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41 ; GCN-NOT: v_mov_b32_e32 v0
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42 ; GCN-NOT: v_mov_b32_e32 v1
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43 ; GCN-NOT: v_mov_b32_e32 v2
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44 ; GCN: v_mov_b32_e32 v3, v4
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45 ; GCN: v_mov_b32_e32 v4, v6
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46 ; GCN-NOT: s_endpgm
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252
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47 define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr0(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {
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150
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48 bb:
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49 %i0 = extractelement <2 x i32> %arg4, i32 0
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50 %i1 = extractelement <2 x i32> %arg4, i32 1
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51 %i2 = extractelement <2 x i32> %arg7, i32 0
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52 %i3 = extractelement <2 x i32> %arg8, i32 0
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53 %f0 = bitcast i32 %i0 to float
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54 %f1 = bitcast i32 %i1 to float
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55 %f2 = bitcast i32 %i2 to float
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56 %f3 = bitcast i32 %i3 to float
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57 %r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
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58 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
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59 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
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60 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
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61 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4
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62 ret { float, float, float, float, float } %r4
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63 }
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64
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65 ; GCN: .long 165580
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66 ; GCN-NEXT: .long 1
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67 ; GCN-NEXT: .long 165584
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68 ; GCN-NEXT: .long 1
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69 ; GCN-LABEL: {{^}}ps_input_ena_no_inputs:
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70 ; GCN: v_mov_b32_e32 v0, 1.0
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71 ; GCN-NOT: s_endpgm
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252
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72 define amdgpu_ps float @ps_input_ena_no_inputs(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {
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150
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73 bb:
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74 ret float 1.000000e+00
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75 }
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76
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77 ; GCN: .long 165580
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78 ; GCN-NEXT: .long 2081
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79 ; GCN-NEXT: .long 165584
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80 ; GCN-NEXT: .long 2081
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81 ; GCN-LABEL: {{^}}ps_input_ena_pos_w:
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82 ; GCN-DAG: v_mov_b32_e32 v0, v4
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83 ; GCN-DAG: v_mov_b32_e32 v1, v2
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84 ; GCN-DAG: v_mov_b32_e32 v2, v3
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85 ; GCN-NOT: s_endpgm
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252
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86 define amdgpu_ps { float, <2 x float> } @ps_input_ena_pos_w(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {
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150
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87 bb:
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88 %f = bitcast <2 x i32> %arg8 to <2 x float>
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89 %s = insertvalue { float, <2 x float> } undef, float %arg14, 0
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90 %s1 = insertvalue { float, <2 x float> } %s, <2 x float> %f, 1
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91 ret { float, <2 x float> } %s1
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92 }
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93
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94 ; GCN: .long 165580
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95 ; GCN-NEXT: .long 562
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96 ; GCN-NEXT: .long 165584
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97 ; GCN-NEXT: .long 563
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98 ; GCN-LABEL: {{^}}vgpr_ps_addr1:
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99 ; GCN-DAG: v_mov_b32_e32 v0, v2
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100 ; GCN-DAG: v_mov_b32_e32 v1, v3
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101 ; GCN: v_mov_b32_e32 v2, v4
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102 ; GCN-DAG: v_mov_b32_e32 v3, v6
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103 ; GCN-DAG: v_mov_b32_e32 v4, v8
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104 ; GCN-NOT: s_endpgm
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252
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105 define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr1(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #2 {
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150
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106 bb:
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107 %i0 = extractelement <2 x i32> %arg4, i32 0
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108 %i1 = extractelement <2 x i32> %arg4, i32 1
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109 %i2 = extractelement <2 x i32> %arg7, i32 0
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110 %i3 = extractelement <2 x i32> %arg8, i32 0
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111 %f0 = bitcast i32 %i0 to float
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112 %f1 = bitcast i32 %i1 to float
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113 %f2 = bitcast i32 %i2 to float
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114 %f3 = bitcast i32 %i3 to float
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115 %r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
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116 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
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117 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
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118 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
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119 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4
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120 ret { float, float, float, float, float } %r4
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121 }
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122
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123 ; GCN: .long 165580
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124 ; GCN-NEXT: .long 562
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125 ; GCN-NEXT: .long 165584
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126 ; GCN-NEXT: .long 631
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127 ; GCN-LABEL: {{^}}vgpr_ps_addr119:
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128 ; GCN-DAG: v_mov_b32_e32 v0, v2
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129 ; GCN-DAG: v_mov_b32_e32 v1, v3
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130 ; GCN-DAG: v_mov_b32_e32 v2, v6
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131 ; GCN-DAG: v_mov_b32_e32 v3, v8
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132 ; GCN-DAG: v_mov_b32_e32 v4, v12
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133 ; GCN-NOT: s_endpgm
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252
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134 define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr119(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #3 {
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150
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135 bb:
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136 %i0 = extractelement <2 x i32> %arg4, i32 0
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137 %i1 = extractelement <2 x i32> %arg4, i32 1
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138 %i2 = extractelement <2 x i32> %arg7, i32 0
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139 %i3 = extractelement <2 x i32> %arg8, i32 0
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140 %f0 = bitcast i32 %i0 to float
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141 %f1 = bitcast i32 %i1 to float
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142 %f2 = bitcast i32 %i2 to float
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143 %f3 = bitcast i32 %i3 to float
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144 %r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
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145 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
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146 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
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147 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
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148 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4
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149 ret { float, float, float, float, float } %r4
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150 }
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151
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152 ; GCN: .long 165580
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153 ; GCN-NEXT: .long 562
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154 ; GCN-NEXT: .long 165584
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155 ; GCN-NEXT: .long 946
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156 ; GCN-LABEL: {{^}}vgpr_ps_addr418:
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157 ; GCN-NOT: v_mov_b32_e32 v0
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158 ; GCN-NOT: v_mov_b32_e32 v1
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159 ; GCN-NOT: v_mov_b32_e32 v2
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160 ; GCN: v_mov_b32_e32 v3, v4
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161 ; GCN: v_mov_b32_e32 v4, v8
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162 ; GCN-NOT: s_endpgm
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252
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163 define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr418(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #4 {
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150
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164 bb:
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165 %i0 = extractelement <2 x i32> %arg4, i32 0
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166 %i1 = extractelement <2 x i32> %arg4, i32 1
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167 %i2 = extractelement <2 x i32> %arg7, i32 0
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168 %i3 = extractelement <2 x i32> %arg8, i32 0
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169 %f0 = bitcast i32 %i0 to float
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170 %f1 = bitcast i32 %i1 to float
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171 %f2 = bitcast i32 %i2 to float
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172 %f3 = bitcast i32 %i3 to float
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173 %r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
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174 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
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175 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
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176 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
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177 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4
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178 ret { float, float, float, float, float } %r4
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179 }
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180
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181 ; GCN-LABEL: {{^}}sgpr:
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182 ; GCN-DAG: s_mov_b32 s2, s3
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183 ; GCN-DAG: s_add_{{i|u}}32 s0, s3, 2
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184 ; GCN-NOT: s_endpgm
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252
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185 define amdgpu_vs { i32, i32, i32 } @sgpr(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
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150
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186 bb:
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187 %x = add i32 %arg2, 2
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188 %a = insertvalue { i32, i32, i32 } undef, i32 %x, 0
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189 %b = insertvalue { i32, i32, i32 } %a, i32 %arg1, 1
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190 %c = insertvalue { i32, i32, i32 } %a, i32 %arg2, 2
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191 ret { i32, i32, i32 } %c
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192 }
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193
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194 ; GCN-LABEL: {{^}}sgpr_literal:
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195 ; GCN: s_mov_b32 s0, 5
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196 ; GCN-NOT: s_mov_b32 s0, s0
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197 ; GCN-DAG: s_mov_b32 s1, 6
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198 ; GCN-DAG: s_mov_b32 s2, 7
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199 ; GCN-DAG: s_mov_b32 s3, 8
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200 ; GCN-NOT: s_endpgm
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252
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201 define amdgpu_vs { i32, i32, i32, i32 } @sgpr_literal(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
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150
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202 bb:
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203 %x = add i32 %arg2, 2
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204 ret { i32, i32, i32, i32 } { i32 5, i32 6, i32 7, i32 8 }
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205 }
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206
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207 ; GCN-LABEL: {{^}}both:
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208 ; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm
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209 ; GCN-DAG: v_mov_b32_e32 v1, v0
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210 ; GCN-DAG: s_mov_b32 s1, s2
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211 ; GCN-DAG: s_waitcnt expcnt(0)
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212 ; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
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213 ; GCN-DAG: s_add_{{i|u}}32 s0, s3, 2
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214 ; GCN-DAG: s_mov_b32 s2, s3
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215 ; GCN-NOT: s_endpgm
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252
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216 define amdgpu_vs { float, i32, float, i32, i32 } @both(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
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150
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217 bb:
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218 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
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219 %v = fadd float %arg3, 1.000000e+00
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220 %s = add i32 %arg2, 2
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221 %a0 = insertvalue { float, i32, float, i32, i32 } undef, float %v, 0
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222 %a1 = insertvalue { float, i32, float, i32, i32 } %a0, i32 %s, 1
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223 %a2 = insertvalue { float, i32, float, i32, i32 } %a1, float %arg3, 2
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224 %a3 = insertvalue { float, i32, float, i32, i32 } %a2, i32 %arg1, 3
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225 %a4 = insertvalue { float, i32, float, i32, i32 } %a3, i32 %arg2, 4
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226 ret { float, i32, float, i32, i32 } %a4
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227 }
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228
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229 ; GCN-LABEL: {{^}}structure_literal:
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230 ; GCN: exp mrt0 v0, v0, v0, v0 done vm
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231
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232 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
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233 ; GCN-DAG: s_mov_b32 s0, 2
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234 ; GCN-DAG: s_mov_b32 s1, 3
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235 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
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236 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
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237 ; GCN-DAG: s_waitcnt expcnt(0)
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252
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238 define amdgpu_vs { { float, i32 }, { i32, <2 x float> } } @structure_literal(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
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150
|
239 bb:
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240 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
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241 ret { { float, i32 }, { i32, <2 x float> } } { { float, i32 } { float 1.000000e+00, i32 2 }, { i32, <2 x float> } { i32 3, <2 x float> <float 2.000000e+00, float 4.000000e+00> } }
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242 }
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243
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244 ; GCN-LABEL: {{^}}ret_return_to_epilog_pseudo_size:
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245 ; GCN: codeLenInByte = 0{{$}}
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246 define amdgpu_ps float @ret_return_to_epilog_pseudo_size() #0 {
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247 ret float undef
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248 }
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249
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250 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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251
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252 attributes #0 = { nounwind }
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253 attributes #1 = { nounwind "InitialPSInputAddr"="0" }
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254 attributes #2 = { nounwind "InitialPSInputAddr"="1" }
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255 attributes #3 = { nounwind "InitialPSInputAddr"="119" }
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256 attributes #4 = { nounwind "InitialPSInputAddr"="418" }
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